74HCT157BQ [NXP]

Quad 2-input multiplexer; 四2输入多路复用器
74HCT157BQ
型号: 74HCT157BQ
厂家: NXP    NXP
描述:

Quad 2-input multiplexer
四2输入多路复用器

解复用器 逻辑集成电路
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中文:  中文翻译
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74HC157; 74HCT157  
Quad 2-input multiplexer  
Rev. 3 — 31 December 2010  
Product data sheet  
1. General description  
The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two  
sources under the control of a common data select input (S). The enable input (E) is  
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of  
all other input conditions.  
Moving the data from two groups of registers to four common output buses is a common  
use of the 74HC/HCT157. The state of the common data select input (S) determines the  
particular register from which the data comes. It can also be used as function generator.  
The device is useful for implementing highly irregular logic by generating any four of the  
16 different functions of two variables with one variable common. The 74HC/HCT157 is  
logic implementation of a 4-pole, 2-position switch, where the position of the switch is  
determine by the logic levels applied to S.  
The logic equations are:  
1Y = E (1I1 S + 1I0 S)  
2Y = E (2I1 S + 2I0 S)  
3Y = E (3I1 S + 3I0 S)  
4Y = E (4I1 S + 4I0 S)  
The 74HC/HCT157 is identical to the 74HC158 but has non-inverting (true) outputs.  
2. Features and benefits  
Low-power dissipation  
Non-inverting data path  
ESD protection:  
HBM JESD22-A114F exceeds 2 000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C and from 40 C to +125 C  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
3. Ordering information  
Table 1.  
Type number Package  
Temperature range Name  
Ordering information  
Description  
Version  
74HC157N  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
DIP16  
plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
74HCT157N  
74HC157D  
SO16  
plastic small outline package; 16 leads; body width  
3.9 mm  
SOT109-1  
SOT338-1  
SOT403-1  
74HCT157D  
74HC157DB  
74HCT157DB  
SSOP16  
TSSOP16  
plastic shrink small outline package; 16 leads;  
body width 5.3 mm  
74HC157PW 40 C to +125 C  
plastic thin shrink small outline package; 16 leads;  
body width 4.4 mm  
74HCT157PW  
74HC157BQ  
40 C to +125 C  
DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1  
thin quad flat package; no leads; 16 terminals;  
74HCT157BQ  
body 2.5 3.5 0.85 mm  
4. Functional diagram  
S
E
1I1  
1Y  
2Y  
1I0  
2I1  
2I0  
2
3
5
6
11 10 14 13  
3I1  
3I0  
3Y  
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1  
1
S
E
15  
4I1  
1Y  
4
2Y  
7
3Y  
9
4Y  
12  
4Y  
4I0  
mna484  
mna481  
Fig 1. Logic diagram  
Fig 2. logic symbol  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
2 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
1
G1  
1I0  
1I1  
2
3
1Y  
2Y  
3Y  
4Y  
4
7
15  
EN  
2I0  
2I1  
3I0  
3I1  
4I0  
5
6
2
1
1
MUX  
4
7
9
3
5
6
MULTIPLEXER  
OUTPUTS  
SELECTOR  
11  
10  
14  
9
11  
10  
12  
13 4I1  
14  
13  
12  
S
1
E
mna483  
15  
mna482  
Fig 3. Logic symbol  
Fig 4. IEC logic symbol  
5. Pinning information  
5.1 Pinning  
74HC157  
74HCT157  
terminal 1  
index area  
74HC157  
74HCT157  
2
3
4
5
6
7
15  
1I0  
1I1  
1Y  
2I0  
2I1  
2Y  
E
14  
13  
12  
11  
10  
4I0  
4I1  
4Y  
3I0  
3I1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
S
1I0  
V
E
CC  
1I1  
4I0  
4I1  
4Y  
3I0  
3I1  
3Y  
1Y  
(1)  
GND  
2I0  
2I1  
2Y  
001aan354  
GND  
Transparent top view  
001aan353  
(1) This is not a supply pin. The substrate is attached to  
this pad using conductive die attach material. There  
is no electrical or mechanical requirement to solder  
this pad. However, if it is soldered, the solder land  
should remain floating or be connected to GND.  
Fig 5. Pin configuration DIP16, SO16, (T)SSOP16  
Fig 6. Pin configuration DHVQFN16  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
3 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
5.2 Pin description  
Table 2.  
Symbol  
S
Pin description  
Pin  
Description  
1
common data select input  
data inputs from source 0  
data inputs from source 1  
multiplexer outputs  
ground (0 V)  
1I0 to 4I0  
1I1 to 4I1  
1Y to 4Y  
GND  
2, 5, 11, 14  
3, 6, 10, 13  
4, 7, 9, 12  
8
E
15  
16  
enable input (active LOW)  
supply voltage  
VCC  
6. Functional description  
Table 3.  
Function table[1]  
Input  
Output  
E
H
L
L
L
L
S
X
L
nI0  
X
nI1  
X
nY  
L
L
X
L
L
H
X
X
H
L
H
H
L
X
H
H
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care.  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
Max  
+7  
Unit  
V
supply voltage  
0.5  
input clamping current  
output clamping current  
output current  
VI < 0.5 V or VI > VCC + 0.5 V  
VO < 0.5 V or VO > VCC + 0.5 V  
VO = 0.5 V to (VCC + 0.5 V)  
-
20  
20  
25  
+50  
50  
+150  
mA  
mA  
mA  
mA  
mA  
C  
IOK  
-
IO  
-
ICC  
supply current  
-
IGND  
Tstg  
Ptot  
ground current  
-
storage temperature  
total power dissipation  
SO16 package  
65  
Tamb = 40 C to +125 C  
[1]  
[2]  
[3]  
-
-
-
500  
500  
500  
mW  
mW  
mW  
TSSOP16 package  
DHVQFN16 package  
[1] Ptot derates linearly with 8 mW/K above 70 C.  
[2] Ptot derates linearly with 5.5 mW/K above 60 C.  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
4 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
[3] Ptot derates linearly with 4.5 mW/K above 60 C.  
8. Recommended operating conditions  
Table 5.  
Recommended operating conditions  
Voltages are referenced to GND (ground = 0 V)  
Symbol Parameter Conditions  
74HC157  
74HCT157  
Unit  
Min  
Typ  
Max  
6.0  
Min  
Typ  
Max  
5.5  
VCC  
VCC  
+125  
-
VCC  
VI  
supply voltage  
2.0  
5.0  
4.5  
5.0  
V
input voltage  
0
-
VCC  
VCC  
+125  
625  
139  
83  
0
-
V
VO  
output voltage  
0
-
0
-
V
Tamb  
t/V  
ambient temperature  
input transition rise and fall rate VCC = 2.0 V  
VCC = 4.5 V  
40  
+25  
40  
+25  
C  
-
-
-
-
-
-
-
-
ns/V  
ns/V  
ns/V  
1.67  
-
1.67  
-
139  
-
VCC = 6.0 V  
9. Static characteristics  
Table 6.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Tamb = 25 C  
Min Typ Max  
Tamb = 40 C to Tamb = 40 C to Unit  
+85 C +125 C  
Min  
Max  
Min  
Max  
74HC157  
VIH  
HIGH-level  
input voltage  
VCC = 2.0 V  
1.5  
1.2  
2.4  
3.2  
0.8  
-
-
1.5  
-
-
1.5  
-
-
V
V
V
V
V
V
VCC = 4.5 V  
3.15  
3.15  
3.15  
VCC = 6.0 V  
4.2  
-
4.2  
-
4.2  
-
VIL  
LOW-level  
input voltage  
VCC = 2.0 V  
-
-
-
0.5  
-
-
-
0.5  
1.35  
1.8  
-
-
-
0.5  
1.35  
1.8  
VCC = 4.5 V  
2.1 1.35  
VCC = 6.0 V  
2.8  
1.8  
VOH  
HIGH-level  
VI = VIH or VIL  
output voltage  
IO = 20 A; VCC = 2.0 V  
IO = 20 A; VCC = 4.5 V  
IO = 20 A; VCC = 6.0 V  
1.9  
4.4  
5.9  
2.0  
4.5  
6.0  
-
-
-
-
-
1.9  
4.4  
-
-
-
-
-
1.9  
4.4  
5.9  
3.7  
5.2  
-
-
-
-
-
V
V
V
V
V
5.9  
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32  
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81  
VI = VIH or VIL  
3.84  
5.34  
VOL  
LOW-level  
output voltage  
IO = 20 A; VCC = 2.0 V  
IO = 20 A; VCC = 4.5 V  
IO = 20 A; VCC = 6.0 V  
IO = 4.0 mA; VCC = 4.5 V  
IO = 5.2 mA; VCC = 6.0 V  
-
-
-
-
-
-
0
0
0
0.1  
0.1  
0.1  
-
-
-
-
-
-
0.1  
0.1  
-
-
-
-
-
-
0.1  
0.1  
0.1  
0.4  
0.4  
1.0  
V
V
0.1  
V
0.15 0.26  
0.16 0.26  
0.33  
0.33  
1.0  
V
V
II  
input leakage  
current  
VI = VCC or GND;  
VCC = 6.0 V  
-
0.1  
A  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
5 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
Table 6.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to Tamb = 40 C to Unit  
+85 C +125 C  
Min Typ  
Max  
Min  
Max  
Min  
Max  
ICC  
CI  
supply current VI = VCC or GND; IO = 0 A;  
CC = 6.0 V  
-
-
8.0  
-
80  
-
160  
A  
V
input  
-
3.5  
-
pF  
capacitance  
74HCT157  
VIH  
HIGH-level  
input voltage  
VCC = 4.5 V to 5.5 V  
VCC = 4.5 V to 5.5 V  
2.0  
-
1.6  
1.2  
-
2.0  
-
-
2.0  
-
-
V
V
VIL  
LOW-level  
0.8  
0.8  
0.8  
input voltage  
VOH  
HIGH-level  
output voltage  
VI = VIH or VIL; VCC = 4.5 V  
IO = 20 A  
4.4  
4.5  
-
-
4.4  
-
-
4.4  
3.7  
-
-
V
V
IO = 4 mA  
3.98 4.32  
3.84  
VOL  
LOW-level  
output voltage  
VI = VIH or VIL; VCC = 4.5 V  
IO = 20 A  
-
-
-
0
0.1  
-
-
-
0.1  
-
-
-
0.1  
0.4  
V
IO = 4.0 mA  
0.15 0.26  
0.33  
1.0  
V
II  
input leakage  
current  
VI = VCC or GND;  
VCC = 5.5 V  
-
0.1  
1.0  
A  
ICC  
ICC  
supply current VI = VCC or GND; IO = 0 A;  
VCC = 5.5 V  
-
-
8.0  
-
80  
-
160  
A  
additional  
VI = VCC 2.1 V;  
supply current other inputs at VCC or GND;  
VCC = 4.5 V to 5.5 V;  
IO = 0 A  
per input pin; nIn inputs  
per input pin; E input  
per input pin; S input  
-
-
-
-
100  
60  
360  
216  
360  
-
-
-
-
450  
270  
450  
-
-
-
490  
294  
490  
A  
A  
A  
pF  
100  
3.5  
CI  
input  
capacitance  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
6 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.  
Symbol Parameter Conditions  
Tamb = 25 C  
Min  
Tamb = 40 C  
to +85 C  
Tamb = 40 C  
to +125 C  
Unit  
Typ Max Min  
Max  
Min  
Max  
For type 74HC157  
[1]  
[1]  
[1]  
tpd  
propagation nI0, nI1 to nY; see Figure 7  
delay  
VCC = 2.0 V  
VCC = 4.5 V  
-
-
-
-
36  
13  
11  
10  
125  
25  
-
-
-
-
-
155  
31  
-
-
-
-
-
190  
38  
-
ns  
ns  
ns  
ns  
VCC = 5 V; CL = 15 pF  
VCC = 6.0 V  
21  
26  
32  
S to nY; see Figure 7  
VCC = 2.0 V  
-
-
-
-
41  
15  
12  
12  
125  
25  
-
-
-
-
-
155  
31  
-
-
-
-
-
190  
38  
-
ns  
ns  
ns  
ns  
VCC = 4.5 V  
VCC = 5 V; CL = 15 pF  
VCC = 6.0 V  
21  
26  
32  
E to nY; see Figure 8  
VCC = 2.0 V  
-
-
-
-
39  
14  
11  
11  
115  
23  
-
-
-
-
-
145  
29  
-
-
-
-
-
175  
35  
-
ns  
ns  
ns  
ns  
VCC = 4.5 V  
VCC = 5 V; CL = 15 pF  
VCC = 6.0 V  
20  
25  
30  
[2]  
[3]  
tt  
transition  
time  
nY; see Figure 7  
VCC = 2.0 V  
-
-
-
-
19  
7
75  
15  
13  
-
-
-
-
-
95  
19  
16  
-
-
-
-
-
110  
22  
19  
-
ns  
ns  
ns  
pF  
VCC = 4.5 V  
VCC = 6.0 V  
6
CPD  
power  
dissipation  
capacitance  
CL = 50 pF; f = 1 MHz;  
VI = GND to VCC  
70  
For type 74HCT157  
[1]  
[1]  
[1]  
tpd  
propagation nI0, nI1 to nY; see Figure 7  
delay  
VCC = 4.5 V  
-
-
16  
13  
27  
-
-
-
34  
-
-
-
41  
-
ns  
ns  
VCC = 5 V; CL = 15 pF  
S to nY; see Figure 7  
VCC = 4.5 V  
-
-
22  
19  
37  
-
-
-
46  
-
-
-
56  
-
ns  
ns  
VCC = 5 V; CL = 15 pF  
E to nY; see Figure 8  
VCC = 4.5 V  
-
-
15  
12  
26  
-
-
-
33  
-
-
-
39  
-
ns  
ns  
VCC = 5 V; CL = 15 pF  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
7 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
Table 7.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.  
Symbol Parameter Conditions  
Tamb = 25 C  
Min  
Tamb = 40 C  
to +85 C  
Tamb = 40 C  
to +125 C  
Unit  
Typ Max Min  
Max  
Min  
Max  
[2]  
[3]  
tt  
transition  
time  
nY; see Figure 7  
VCC = 4.5 V  
-
-
7
15  
-
-
-
19  
-
-
-
22  
-
ns  
CPD  
power  
dissipation  
capacitance  
CL = 50 pF; f = 1 MHz;  
VI = GND to VCC  
70  
pF  
[1] tpd is the same as tPLH and tPHL  
[2] tt is the same as tTHL and tTLH  
[3] PD is used to determine the dynamic power dissipation (PD in W).  
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL VCC2 fo) = sum of outputs.  
11. Waveforms  
V
I
nI0, nI1, S  
input  
V
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
mna486  
V
OL  
Measurement points are given in Table 8.  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 7. Propagation delay input (nI0, nI1, S) to output (nYn)  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
8 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
V
CC  
V
E input  
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
mna485  
V
OL  
Measurement points are given in Table 8.  
OL and VOH are typical voltage output levels that occur with the output load.  
V
Fig 8. Propagation delay input (E) to output (nY)  
Table 8.  
Type  
Measurement points  
Input  
VM  
Output  
VM  
74HC157  
0.5VCC  
1.3 V  
0.5VCC  
1.3 V  
74HCT157  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
9 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
GND  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
GND  
t
W
V
CC  
V
V
O
I
G
DUT  
R
T
C
L
001aah768  
Test data is given in Table 9.  
Definitions test circuit:  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including jig and probe capacitance.  
RL = Load resistance.  
S1 = Test selection switch.  
Fig 9. Test circuit for measuring switching times  
Table 9.  
Type  
Test data  
Input  
VI  
Load  
Test  
tr, tf  
CL  
74HC157  
VCC  
3.0 V  
6.0 ns  
6.0 ns  
15 pF, 50 pF  
15 pF, 50 pF  
tPLH, tPHL  
tPLH, tPHL  
74HCT157  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
10 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
12. Package outline  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 10. Package outline SOT109-1 (SO16)  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
11 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm  
SOT338-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
8
1
detail X  
w M  
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.00  
0.55  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT338-1  
MO-150  
Fig 11. Package outline SOT338-1 (SSOP16)  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
12 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT403-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
8
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.40  
0.06  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT403-1  
MO-153  
Fig 12. Package outline SOT403-1 (TSSOP16)  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
13 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;  
16 terminals; body 2.5 x 3.5 x 0.85 mm  
SOT763-1  
B
A
D
A
A
1
E
c
detail X  
terminal 1  
index area  
C
terminal 1  
index area  
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16  
15  
10  
D
h
X
0
2.5  
scale  
5 mm  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.  
0.05 0.30  
0.00 0.18  
3.6  
3.4  
2.15  
1.85  
2.6  
2.4  
1.15  
0.85  
0.5  
0.3  
mm  
0.05  
0.1  
1
0.2  
0.5  
2.5  
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-10-17  
03-01-27  
SOT763-1  
- - -  
MO-241  
- - -  
Fig 13. Package outline SOT763-1 (DHVQFN16)  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
14 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
13. Abbreviations  
Table 10. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MM  
Machine Model  
TTL  
Transistor-Transistor Logic  
14. Revision history  
Table 11. Revision history  
Document ID  
Release date Data sheet status  
20101231 Product data sheet  
Change notice  
Supersedes  
74HC_HCT157 v.3  
Modifications:  
-
74HC_HCT157_CNV v.2  
The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
Legal texts have been adapted to the new company name where appropriate.  
Section 3: DHVQFN16 package added.  
Section 7: derating values added for DHVQFN16 package.  
Section 12: outline drawing added for DHVQFN16 package.  
74HC_HCT157_CNV v.2  
19970827  
Product specification  
-
-
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
15 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
suitable for use in medical, military, aircraft, space or life support equipment,  
15.2 Definitions  
nor in applications where failure or malfunction of an NXP Semiconductors  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. NXP Semiconductors accepts no  
liability for inclusion and/or use of NXP Semiconductors products in such  
equipment or applications and therefore such inclusion and/or use is at the  
customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Suitability for use in automotive applications — This NXP  
Semiconductors product has been qualified for use in automotive  
applications. The product is not designed, authorized or warranted to be  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
16 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74HC_HCT157  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 3 — 31 December 2010  
17 of 18  
74HC157; 74HCT157  
NXP Semiconductors  
Quad 2-input multiplexer  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
6
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 17  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2010.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 31 December 2010  
Document identifier: 74HC_HCT157  

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