74HCT175D,652 [NXP]
74HC(T)175 - Quad D-type flip-flop with reset; positive-edge trigger SOP 16-Pin;![74HCT175D,652](http://pdffile.icpdf.com/pdf2/p00266/img/icpdf/74HC175N-652_1601541_icpdf.jpg)
型号: | 74HCT175D,652 |
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描述: | 74HC(T)175 - Quad D-type flip-flop with reset; positive-edge trigger SOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
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74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 8 April 2014
Product data sheet
1. General description
The 74HC175; 74HCT175 are quad positive edge-triggered D-type flip-flops with
individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is
stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and
outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are
required and the clock and master reset are common to all storage elements.
2. Features and benefits
Input levels:
For 74HC175: CMOS level
For 74HCT175: TTL level
Four edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC175N
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT175N
74HC175D
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
SOT338-1
SOT403-1
74HCT175D
74HC175DB
74HCT175DB
74HC175PW
74HCT175PW
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
ꢄ
&ꢁ
ꢁ
5
ꢄ
ꢂ
ꢂ
ꢃ
&3
4ꢀ
4ꢀ
4ꢁ
4ꢁ
4ꢂ
4ꢂ
4ꢃ
4ꢃ
ꢆ
ꢆ
ꢁ'
ꢃ
'ꢀ
'ꢁ
'ꢂ
'ꢃ
ꢇ
ꢇ
ꢈ
ꢅ
ꢅ
ꢈ
ꢁꢀ
ꢁꢁ
ꢁꢅ
ꢁꢆ
ꢁꢂ
ꢁꢃ
ꢁꢀ
ꢁꢁ
ꢁꢂ
ꢁꢃ
ꢁꢅ
ꢁꢆ
05
ꢁ
DDDꢀꢁꢁꢂꢃꢄꢅ
DDDꢀꢁꢁꢂꢃꢄꢄ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
'ꢀ
'ꢁ
'ꢂ
'ꢃ
'
4
))ꢁ
4
'
4
))ꢂ
4
'
4
))ꢃ
4
'
4
))ꢆ
&3
&3
&3
&3
4
5'
5'
5'
5'
&3
05
4ꢀ
4ꢀ
4ꢁ
4ꢁ
4ꢂ
4ꢂ
4ꢃ
4ꢃ
DDDꢀꢁꢁꢂꢃꢄꢆ
Fig 3. Logic diagram
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
2 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢀꢃ
ꢀꢁ+&7ꢂꢀꢃ
ꢀꢁ+&ꢂꢀꢃ
ꢀꢁ+&7ꢂꢀꢃ
ꢁꢈ
ꢁꢅ
ꢁꢆ
ꢁꢃ
ꢁꢂ
ꢁꢁ
ꢁꢀ
ꢄ
ꢁ
ꢂ
ꢃ
ꢆ
ꢅ
ꢈ
ꢇ
ꢉ
05
4ꢀ
9
&&
ꢁ
ꢂ
ꢃ
ꢆ
ꢅ
ꢈ
ꢇ
ꢉ
ꢁꢈ
ꢁꢅ
ꢁꢆ
ꢁꢃ
ꢁꢂ
ꢁꢁ
ꢁꢀ
ꢄ
05
4ꢀ
9
&&
ꢀꢁ+&ꢂꢀꢃ
ꢀꢁ+&7ꢂꢀꢃ
4ꢃ
4ꢃ
'ꢃ
'ꢂ
4ꢂ
4ꢂ
&3
4ꢃ
4ꢃ
'ꢃ
'ꢂ
4ꢂ
4ꢂ
&3
4ꢀ
4ꢀ
ꢁ
ꢂ
ꢃ
ꢆ
ꢅ
ꢈ
ꢇ
ꢉ
ꢁꢈ
ꢁꢅ
ꢁꢆ
ꢁꢃ
ꢁꢂ
ꢁꢁ
ꢁꢀ
ꢄ
05
4ꢀ
9
&&
'ꢀ
4ꢃ
4ꢃ
'ꢃ
'ꢂ
4ꢂ
4ꢂ
&3
'ꢀ
4ꢀ
'ꢁ
'ꢁ
'ꢀ
4ꢁ
4ꢁ
'ꢁ
4ꢁ
4ꢁ
4ꢁ
4ꢁ
*1'
*1'
*1'
DDDꢀꢁꢁꢂꢃꢄꢂ
DDDꢀꢁꢁꢂꢃꢄꢃ
DDDꢀꢁꢁꢂꢃꢇꢁ
Fig 4. Pin configuration DIP16
Fig 5. Pin configuration SO16
Fig 6. Pin configuration SSOP16
and TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
Pin description
Pin
Description
1
asynchronous master reset input (active LOW)
flip-flop output
Q0 to Q3
Q0 to Q3
D0 to D3
GND
2, 7, 10, 15
3, 6, 11, 14
complementary flip-flop output
data input
4, 5, 12, 13
8
ground (0 V)
CP
9
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
VCC
16
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
3 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Outputs
MR
L
CP
X
Dn
X
h
Qn
L
Qn
H
reset (clear)
load “1”
H
H
L
load “0”
H
l
L
H
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
ꢆ
ꢅ
ꢁꢂ
ꢁꢃ
'ꢀ
'ꢁ
'ꢂ
'ꢃ
'
4
))ꢁ
4
'
4
))ꢂ
4
'
4
))ꢃ
4
'
4
))ꢆ
4
&3
&3
&3
&3
5'
5'
5'
5'
ꢄ
ꢁ
&3
05
4ꢀ
ꢃ
4ꢀ
ꢂ
4ꢁ
ꢈ
4ꢁ
ꢇ
4ꢂ
ꢁꢁ
4ꢂ
ꢁꢀ
4ꢃ
ꢁꢆ
4ꢃ
ꢁꢅ
DDDꢀꢁꢁꢂꢃꢇꢅ
Fig 7. Functional diagram
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
ground current
50
65
-
storage temperature
+150
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
4 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Conditions
Min
Max
Unit
Ptot
total power dissipation
Tamb = 40 C to +125 C
DIP16 package
[1]
[2]
-
-
750
500
mW
mW
SO16, SSOP16 and TSSOP16
[1] For DIP16 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
[2] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC175
74HCT175
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
-
-
-
V
VO
output voltage
0
-
0
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
C
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
74HC175
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
-
1.5
-
-
-
1.5
-
-
-
V
V
V
V
V
V
3.15 2.4
-
3.15
3.15
4.2
3.2
0.8
2.1
2.8
-
4.2
4.2
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
-
-
-
0.5
1.35
1.8
1.35
1.8
VOH
HIGH-level
output voltage
IO = 20 A; VCC = 2.0 V 1.9
IO = 20 A; VCC = 4.5 V 4.4
IO = 20 A; VCC = 6.0 V 5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
4.4
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
3.84
5.34
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
5 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
-
0.1
V
0.1
0.1
0.1
0.4
0.4
1
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
-
0.1
8.0
-
A
V
CC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
A
V
input
3.5
pF
capacitance
74HCT175
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 5.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
CC = 4.5 V to 5.5 V
per input pin;
V
Dn input
CP input
MR input
-
-
-
-
40
60
144
216
-
-
-
-
180
270
450
-
-
-
-
-
196
294
490
-
A
A
A
pF
100 360
3.5
CI
input
-
capacitance
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
6 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 11
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74HC175
[1]
tpd
propagation
delay
CP to Qn, Qn;
see Figure 8
VCC = 2.0 V
-
-
-
-
55
20
17
16
175
35
-
-
-
-
-
220
-
-
-
-
265
ns
ns
ns
ns
VCC = 4.5 V
44
-
53
-
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
37
45
tPHL
HIGH to LOW
propagation
delay
MR to Qn, Qn;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
-
-
-
-
50
18
15
14
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
38
[2]
tt
transition time
pulse width
Qn output; see Figure 8
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
CP input HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
MR input LOW;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
6
17
20
trec
recovery time
set-up time
MR to CP; see Figure 10
VCC = 2.0 V
5
5
5
33
12
10
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tsu
Dn to CP; see Figure 8
VCC = 2.0 V
80
16
14
3
1
1
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
17
20
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
7 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 11
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
th
hold time
Dn to CP; see Figure 8
VCC = 2.0 V
25
5
2
0
0
-
-
-
30
-
-
-
40
-
-
-
ns
ns
ns
VCC = 4.5 V
6
5
8
7
VCC = 6.0 V
4
fmax
maximum
frequency
CP input; see Figure 8
VCC = 2.0 V
6
25
75
83
89
32
-
-
4.8
24
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
20
-
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
-
-
-
35
-
-
-
28
-
24
-
[3]
[1]
CPD
power
dissipation
capacitance
per package;
VI = GND to VCC
74HCT175
tpd
propagation
delay
CP to Qn, Qn;
see Figure 8
VCC = 4.5 V
-
-
19
16
33
-
-
-
41
-
-
-
50
-
ns
ns
VCC = 5 V; CL = 15 pF
MR to Qn; see Figure 10
VCC = 4.5 V
tPHL
HIGH to LOW
propagation
delay
-
-
22
19
38
-
-
-
48
-
-
-
57
-
ns
ns
VCC = 5 V; CL = 15 pF
MR to Qn; see Figure 10
VCC = 4.5 V
-
-
19
16
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
Qn output; see Figure 8
VCC = 4.5 V
[2]
tt
transition time
pulse width
-
7
15
-
-
19
-
-
22
-
ns
ns
tW
CP input; see Figure 8
VCC = 4.5 V
20
12
25
30
MR input LOW;
see Figure 10
VCC = 4.5 V
20
5
11
10
5
-
-
-
-
25
5
-
-
-
-
30
5
-
-
-
-
ns
ns
ns
ns
trec
tsu
th
recovery time
set-up time
hold time
MR to CP; see Figure 10
VCC = 4.5 V
Dn to CP; see Figure 8
VCC = 4.5 V
16
5
20
5
24
5
Dn to CP; see Figure 8
VCC = 4.5 V
0
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
8 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 11
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
fmax
maximum
frequency
CP input; see Figure 8
VCC = 4.5 V
25
49
54
34
-
-
20
-
-
-
17
-
-
-
MHz
MHz
pF
VCC = 5 V; CL = 15 pF
-
-
-
-
-
[3]
CPD
power
per package;
-
-
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
ꢁꢊI
PD[
9
,
9
&3ꢋLQSXW
*1'
0
W
:
W
W
3/+
3+/
9
2+
9
4QꢋRXWSXW
0
9
2/
W
W
W
W
7+/
7/+
7/+
W
W
3+/
3/+
9
2+
4QꢋRXWSXW
9
0
9
2/
7+/
DDDꢀꢁꢁꢂꢃꢇꢄ
Measurement points are given in Table 8.
Fig 8. Input to output propagation delay, output transition time, clock input pulse width and maximum
frequency
74HC_HCT175
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Product data sheet
Rev. 4 — 8 April 2014
9 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
9
,
&3ꢋLQSXW
*1'
9
0
W
VX
W
VX
W
W
K
K
9
,
'QꢋLQSXW
*1'
9
0
9
2+
9
9
4QꢋRXWSXW
0
9
2/
9
2+
4QꢋRXWSXW
0
9
2/
DDDꢀꢁꢁꢂꢃꢇꢇ
Measurement points are given in Table 8.
Fig 9. Data set-up and hold times for data input
9
,
9
0
05ꢋLQSXW
*1'
W
:
W
UHP
9
,
9
0
&3ꢋLQSXW
*1'
W
W
3+/
9
2+
9
0
0
4QꢋRXWSXW
9
2/
3/+
9
2+
9
4QꢋRXWSXW
9
2/
DDDꢀꢁꢁꢂꢃꢇꢈ
Measurement points are given in Table 8.
Fig 10. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery
time
Table 8.
Type
Measurement points
Input
Output
VM
VI
VM
74HC175
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT175
74HC_HCT175
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Product data sheet
Rev. 4 — 8 April 2014
10 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 11. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
6 ns
6 ns
CL
RL
74HC175
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
tPLH, tPHL
tPLH, tPHL
74HCT175
74HC_HCT175
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
11 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 12. Package outline SOT38-4 (DIP16)
74HC_HCT175
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Product data sheet
Rev. 4 — 8 April 2014
12 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74HC_HCT175
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
13 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 14. Package outline SOT338-1 (SSOP16)
74HC_HCT175
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
14 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
74HC_HCT175
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
15 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20140408
Data sheet status
Change notice
Supersedes
74HC_HCT175 v.4
Modifications:
Product data sheet
-
74HC_HCT175 v.3
• General description corrected (errata).
20140331 Product data sheet
74HC_HCT175 v.3
Modifications:
-
74HC_HCT175_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT175_CNV_2
19980708
Product specification
-
-
74HC_HCT175
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Product data sheet
Rev. 4 — 8 April 2014
16 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT175
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Product data sheet
Rev. 4 — 8 April 2014
17 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2014
18 of 19
74HC175; 74HCT175
NXP Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 April 2014
Document identifier: 74HC_HCT175
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![](http://pdffile.icpdf.com/pdf1/p00083/img/page/74HCT175_436774_files/74HCT175_436774_2.jpg)
74HCT175NB
IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, FF/Latch
NXP
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