74HCT181N3 [NXP]
4-bit arithmetic logic unit; 4位算术逻辑单元
| 型号： | 74HCT181N3 |
| 厂家： | 
NXP |
| 描述： | 4-bit arithmetic logic unit |
| 文件： | 总20页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT181
4-bit arithmetic logic unit
1998 Jun 10
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
When speed requirements are not stringent, it can be used
in a simple ripple carry mode by connecting the carry
output (Cn+4) signal to the carry input (Cn) of the next unit.
FEATURES
• Full carry look-ahead for high-speed arithmetic
operation on long words
For high-speed operation the device is used in conjunction
with the “182” carry look-ahead circuit. One carry
look-ahead package is required for each group of four
“181” devices. Carry look-ahead can be provided at
various levels and offers high-speed capability over
extremely long word lengths.
• Provides 16 arithmetic operations: add, subtract,
compare, double, plus 12 others
• Provides all 16 logic operations of two variables:
EXCLUSIVE-OR, compare, AND, NAND, NOR, OR plus
10 other logic operations
• Output capability:
standard,
A=B open drain
The comparator output (A=B) of the device goes HIGH
when all four function outputs (F0 to F3) are HIGH and can
be used to indicate logic equivalence over 4 bits when the
unit is in the subtract mode. A=B is an open collector
output and can be wired-AND with other A=B outputs to
give a comparison for more than 4 bits. The open drain
output A=B should be used with an external pull-up
resistor in order to establish a logic HIGH level. The A=B
signal can also be used with the Cn+4 signal to indicate
A > B and A < B.
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT181 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT181 are 4-bit high-speed parallel
Arithmetic Logic Units (ALU). Controlled by the four
function select inputs (S0 to S3) and the mode control input
(M), they can perform all the 16 possible logic operations
or 16 different arithmetic operations on active HIGH or
active LOW operands (see function table).
The function table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus, select code LHHL generates
A minus B minus 1 (2s complement notation) without a
carry in and generates A minus B when a carry is applied.
Because subtraction is actually performed by
complementary addition (1s complement), a carry out
means borrow; thus, a carry is generated when there is no
under-flow and no carry is generated when there is
underflow.
When the mode control input (M) is HIGH, all internal
carries are inhibited and the device3 performs logic
operations on the individual bits as listed. When M is LOW,
the carries are enabled and the “181” performs arithmetic
operations on the two 4-bit words. The “181” incorporates
full internal carry look-ahead and provides for either ripple
carry between devices using the Cn+4 output, or for carry
look-ahead between packages using the carry
As indicated, the “181” can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs.
For either case the table lists the operations that are
performed to the operands.
propagation (P) and carry generate (G) signals. P and
G are not affected by carry in.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
74HC181N3;
74HCT181N3
DIP24
DIP24
SO24
plastic dual in-line package; 24 leads (300 mil)
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width 7.5 mm
SOT222-1
74HC181N;
74HCT181N
SOT101-1
SOT137-1
74HC181D;
74HCT181D
1998 Jun 10
2
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
HCT
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
An or Bn to A=B
Cn to Cn+4
28
17
3.5
90
30
21
3.5
92
ns
ns
pF
pF
CI
input capacitance
CPD
power dissipation capacitance notes 1 and 2
per L package
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
A
B
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 22, 20, 18
B0 to B3
A0 to A3
S0 to S3
Cn
operand inputs (active LOW)
operand inputs (active LOW)
select inputs
2, 23, 21, 19
6, 5, 4, 3
7
carry input
8
M
mode control input
9, 10, 11, 13
F0 to F3
GND
A=B
function outputs (active LOW)
ground (0 V)
12
14
15
16
17
24
comparator output
P
carry propagate output (active LOW)
carry output
Cn+4
G
carry generate output (active LOW)
positive supply voltage
VCC
k, halfpage
F
A
A
A
A
2
23
21
19
9
0
1
2
3
0
1
2
3
F
F
F
10
11
13
B
B
B
B
C
n+4
1
22
20
18
16
0
1
2
3
A=B 14
G
P
17
15
C
7
n
S
6
5
4
3
8
0
1
2
3
S
S
S
M
MBK219
Fig.4 Functional diagram.
Fig.5 Active HIGH operands - active LOW operands.
4
1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
FUNCTION TABLES
MODE SELECT
INPUTS
ACTIVE LOW INPUTS AND
OUTPUTS
MODE SELECT
INPUTS
ACTIVE HIGH INPUTS AND
OUTPUTS
ARITHMETIC(2)
(M=L; Cn=H)
LOGIC
(M=H)
ARITHMETIC(2)
(M=L; Cn=L)
LOGIC
(M=H)
S3
S2
S1
S0
S3
S2
S1
S0
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
A
AB
A minus 1
AB minus 1
AB minus 1
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
A
A + B
AB
A
A + B
A + B
A + B
logical 1 minus 1
H
H
logical 0 minus 1
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
A + B
B
A plus (A + B)
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
AB
B
A
A plus AB
AB plus (A + B)
A minus B minus 1
A + B
(A + B) plus AB
A minus B minus 1
AB minus 1
A
B
B
H
A + B
H
AB
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
AB
A
B
A + B
A plus (A + B)
A plus B
AB plus (A + B)
A + B
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
A + B
A plus AB
A plus B
(A + B) plus AB
AB minus 1
B
A
B
B
AB
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
logical 0 A plus A(1)
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
logical 1 A plus A(1)
AB
AB
A
AB plus A
AB plus A
A
A + B
A + B
A
(A + B) plus A
(A + B) plus A
A minus 1
H
H
Notes to the function tables
Notes to the function tables
1. Each bit is shifted to the next more significant position. 1. Each bit is shifted to the next more significant position.
2. Arithmetic operations expressed in 2s complement
notation.
2. Arithmetic operations expressed in 2s complement
notation.
H = HIGH voltage level
L = LOW voltage level
H = HIGH voltage level
L = LOW voltage level
1998 Jun 10
5
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Fig.6 Logic diagram.
6
1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Table 1 SUM MODE TEST
Function inputs S0 = S3 = 4.5 V, M = S1 = S2 = 0 V
INPUT OTHER INPUT, SAME BIT
PARAMETER UNDER
Apply 4.5 V Apply GND
TEST
OTHER DATA INPUTS
Apply 4.5 V Apply GND
OUTPUT
UNDER
TEST
t
PLH/ tPHL
tPLH/ tPHL
tPLH/ tPHL
PLH/ tPHL
tPLH/ tPHL
Ai
Bi
Ai
Bi
Ai
Bi
Ai
Bi
Cn
Bi
none
none
none
none
Bi
remaining A and B Cn
remaining A and B Cn
Fi
Fi
P
Ai
Bi
none
remaining A and B, Cn
t
Ai
none
remaining A and B, Cn
remaining A, Cn
remaining A, Cn
remaining A, Cn
remaining A, Cn
all B
P
none
none
none
none
none
remaining B
remaining B
remaining B
remaining B
all A
G
G
t
PLH/ tPHL
PLH/ tPHL
Ai
t
Bi
Cn+4
tPLH/ tPHL
tPLH/ tPHL
Ai
Cn+4
none
any F or Cn+4
Table 2 DIFFERENTIAL MODE TEST
Function inputs S1 = S2 = 4.5 V, M = S0 = S3 = 0 V
INPUT OTHER INPUT, SAME BIT
PARAMETER UNDER
Apply 4.5 V Apply GND
TEST
OTHER DATA INPUTS
OUTPUT
UNDER
TEST
Apply 4.5 V
Apply GND
t
PLH/ tPHL
Ai
Bi
Ai
Bi
Ai
Bi
Ai
Bi
Ai
Bi
Cn
none
Ai
Bi
remaining A
remaining A
none
remaining B, Cn
Fi
tPLH/ tPHL
tPLH/ tPHL
tPLH/ tPHL
none
Bi
remaining B, Cn
Fi
none
Ai
remaining A and B, Cn
remaining A and B, Cn
remaining A and B, Cn
remaining A and B, Cn
remaining B, Cn
P
none
none
Ai
none
P
tPLH/ tPHL
tPLH/ tPHL
Bi
none
G
none
none
Ai
none
G
tPLZ/ tPZL
tPLZ/ tPZL
tPLH/ tPHL
Bi
remaining A
remaining A
none
A=B
A=B
none
none
Ai
remaining B, Cn
Bi
remaining A and B, Cn Cn+4
remaining A and B, Cn Cn+4
tPLH/ tPHL
tPLH/ tPHL
none
none
none
none
all A and B
none
any F or Cn+4
Table 3 LOGIC MODE TEST
Function inputs M = S1 = S2 = 4.5 V, S0 = S3 = 0 V
INPUT OTHER INPUT, SAME BIT
PARAMETER UNDER
Apply 4.5 V Apply GND
TEST
OTHER DATA INPUTS
Apply 4.5 V Apply GND
OUTPUT
UNDER
TEST
tPLH/ tPHL
tPLH/ tPHL
Ai
Bi
Bi
Ai
none
none
none
none
remaining A and B, Cn Fi
remaining A and B, Cn Fi
1998 Jun 10
7
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
RATINGS (for A=B output only)
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltage are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
DC output voltage
MIN.
−0.5
MAX.
+7.0
UNIT
CONDITIONS
VO
V
−IOK
−IO
DC output diode current
20
25
mA
mA
for VO < −0.5 V
for −0.5 V < VO
DC output source or sink current
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VIL OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min.
max.
2.0
to
6.0
HIGH level output
leakage current
note 1
VO = 0 or 6 V
IOZ
0.5
5.0
10.0
µA
VIL
Note to the DC characteristics
1. The maximum operating output voltage (VO(max)) is 6.0 V.
1998 Jun 10
8
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
MODE OTHER
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Cn to Cn+4
55 165
20 33
16 28
205
41
35
250 ns
50
43
2.0
4.5
6.0
M = 0 V;
sum
Fig.9;
diff
Tables 1 and 2
t
t
t
t
PHL/ tPLH propagation delay
69 200
25 40
20 34
250
50
43
300 ns
60
51
2.0
4.5
6.0
M = 0 V;
Fig.9;
Tables 1 and 2
sum
diff
Cn to Fn
PHL/ tPLH propagation delay
An to G
72 210
26 42
21 36
265
53
45
315 ns
63
54
2.0
4.5
6.0
M = S1 = S2 = 0 V;
sum
S0 = S3 = 4.5 V;
Fig.7; Table 1
PHL/ tPLH propagation delay
Bn to G
77 230
28 46
22 39
290
58
49
345 ns
69
59
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
PHL/ tPLH propagation delay
An to G
76 215
26 43
21 37
270
54
46
320 ns
65
55
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
tPHL/ tPLH propagation delay
Bn to G
77 240
28 48
22 41
300
60
51
360 ns
72
61
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
tPHL/ tPLH propagation delay
An to P
61 185
22 37
18 31
230
46
39
280 ns
56
48
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
tPHL/ tPLH propagation delay
Bn to P
63 195
23 39
18 33
245
49
42
295 ns
59
50
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
tPHL/ tPLH propagation delay
An to P
55 170
20 34
16 29
215
43
37
255 ns
51
43
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
t
t
t
t
t
PHL/ tPLH propagation delay
63 195
23 39
18 33
245
49
42
295 ns
59
50
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
Bn to P
PHL/ tPLH propagation delay
Ai to Fi
77 230
28 46
22 39
290
58
49
345 ns
69
59
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
PHL/ tPLH propagation delay
Bi to Fi
85 255
31 51
25 43
320
64
54
385 ns
77
65
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
PHL/ tPLH propagation delay
Ai to Fi
77 235
28 47
22 40
295
59
50
355 ns
71
60
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
PHL/ tPLH propagation delay
Bi to Fi
83 255
31 51
24 43
320
64
54
385 ns
77
65
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
1998 Jun 10
9
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
T
amb (°C)
TEST CONDITIONS
MODE OTHER
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Ai to Fi
74 230
27 46
22 39
290
58
49
345 ns
69
59
2.0
M = 4.5 V;
4.5 logic Fig.8;
6.0
Table 3
tPHL/ tPLH propagation delay
Bi to Fi
83 255
30 51
24 43
320
64
54
385 ns
77
65
2.0
M = 4.5 V;
4.5 logic Fig.8;
6.0
Table 3
t
PHL/ tPLH propagation delay
80 235
29 47
23 40
295
59
50
355 ns
71
60
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.8; Table 1
An to Cn+4
tPHL/ tPLH propagation delay
Bn to Cn+4
80 235
29 47
23 40
295
59
50
355 ns
71
60
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.8; Table 1
t
t
t
t
t
PHL/ tPLH propagation delay
77 235
28 47
22 40
295
59
50
355 ns
71
60
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.10; Table 2
An to Cn+4
PHL/ tPLH propagation delay
Bn to Cn+4
85 255
31 51
25 43
320
64
54
385 ns
77
65
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.10; Table 2
PZL/ tPLZ propagation delay
An to A=B
80 245
29 49
23 42
305
61
52
370 ns
74
63
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.11; Table 2
PZL/ tPLZ propagation delay
Bn to A=B
88 270
32 54
26 46
340
68
58
405 ns
81
69
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.11; Table 2
PHL/ tPLH propagation delay
An to Fn
83 255
30 51
24 43
320
64
54
385 ns
77
65
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
tPHL/ tPLH propagation delay
Bn to Fn
85 265
31 53
25 45
330
66
56
400 ns
80
68
2.0
4.5 sum
6.0
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
tPHL/ tPLH propagation delay
An to Fn
77 240
28 48
22 41
300
60
51
360 ns
72
61
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
tPHL/ tPLH propagation delay
Bn to Fn
88 275
32 55
26 47
345
69
59
415 ns
83
71
2.0
4.5 diff
6.0
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
tTHL/ tTLH output transition
time
19 75
95
19
16
110 ns
22
19
2.0
4.5
6.0
note ;
Figs 7 and 11
7
6
15
13
Note to the AC characteristics
1. For the open drain output (A=B) only tTHL is valid.
1998 Jun 10
10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
VIL OTHER
74HCT
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
IOZ
HIGH level output
leakage current
0.5
5.0
10.0 µA
2.0
to
VIL
note 1
VO = 0 or 6 V
6.0
Note to the DC characteristics
1. The maximum operating output voltage (VO(max)) is 6.0 V.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Cn, M
An, Bn
Sn
0.50
0.75
1.00
1998 Jun 10
11
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
MODE OTHER
74HCT
SYMBOL PARAMETER
+25
UNIT
VCC
(V)
−40 to +85 −40 to +125
min. typ. max. min. max. min.
25 42
max.
63
tPHL/ tPLH propagation
delay
53
60
68
68
68
68
51
51
50
50
73
73
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 sum
diff
M = 0 V;
Fig.9;
Tables 1 and 2
Cn to Cn+4
tPHL/ tPLH propagation
28 48
31 54
32 54
31 54
31 54
23 41
24 41
23 40
23 40
33 58
34 58
72
81
81
81
81
62
62
60
60
87
87
4.5 sum
diff
M = 0 V;
Fig.9;
Tables 1 and 2
delay
Cn to Fn
t
t
t
t
t
t
PHL/ tPLH propagation
4.5 sum
4.5 sum
4.5 diff
4.5 diff
4.5 sum
4.5 sum
4.5 diff
4.5 diff
4.5 sum
4.5 sum
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
An to G
PHL/ tPLH propagation
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
Bn to G
PHL/ tPLH propagation
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
An to G
PHL/ tPLH propagation
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
Bn to G
PHL/ tPLH propagation
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
An to P
PHL/ tPLH propagation
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
Bn to P
tPHL/ tPLH propagation
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
An to P
t
PHL/ tPLH propagation
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
Bn to P
tPHL/ tPLH propagation
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
Ai to Fi
t
PHL/ tPLH propagation
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
delay
Bi to Fi
1998 Jun 10
12
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Tamb (°C)
TEST CONDITIONS
MODE OTHER
74HCT
SYMBOL PARAMETER
+25
UNIT
VCC
(V)
−40 to +85 −40 to +125
min. typ. max. min. max. min.
33 57
max.
86
tPHL/ tPLH propagation
71
71
68
68
66
66
69
69
75
75
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 diff
4.5 diff
4.5 logic
4.5 logic
4.5 sum
4.5 sum
4.5 diff
4.5 diff
4.5 diff
4.5 diff
4.5 sum
4.5 sum
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
Ai to Fi
tPHL/ tPLH propagation
33 57
29 54
33 54
30 53
31 53
30 55
34 55
34 60
35 60
33 56
33 56
86
81
81
80
80
83
83
90
90
84
84
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
Bi to Fi
t
PHL/ tPLH propagation
M = 4.5 V;
Fig.8; Table 3
delay
Ai to Fi
tPHL/ tPLH propagation
M = 4.5 V;
Fig.8; Table 3
delay
Bi to Fi
tPHL/ tPLH propagation
delay
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.8; Table 1
An to Cn+4
t
t
t
t
PHL/ tPLH propagation
delay
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.8; Table 1
Bn to Cn+4
PHL/ tPLH propagation
delay
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.10; Table 2
An to Cn+4
PHL/ tPLH propagation
delay
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.10; Table 2
Bn to Cn+4
PZL/ tPLZ propagation
delay
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.11; Table 2
An to A=B
tPZL/ tPLZ propagation
delay
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.11; Table 2
Bn to A=B
t
t
PHL/ tPLH propagation
delay
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
An to Fn
PHL/ tPLH propagation
delay
M = S1 = S2 = 0 V;
S0 = S3 = 4.5 V;
Fig.7; Table 1
Bn to Fn
1998 Jun 10
13
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
T
amb (°C)
TEST CONDITIONS
MODE OTHER
74HCT
SYMBOL PARAMETER
+25
UNIT
VCC
(V)
−40 to +85 −40 to +125
min. typ. max. min. max. min.
max.
84
tPHL/ tPLH propagation
32 56
70
70
19
ns
ns
ns
4.5 diff
4.5 diff
4.5
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
An to Fn
tPHL/ tPLH propagation
33 56
84
22
M = S0 = S3 = 0 V;
S1 = S2 = 4.5 V;
Fig.8; Table 2
delay
An to Fn
t
THL/ tTLH output
transition time
7
15
Figs 7 and 11;
note 1
Note to the AC characteristics
1. For the open drain output (A=B) only tTHL is valid.
1998 Jun 10
14
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
AC WAVEFORMS
Fig.7 Propagation delays for carry input to carry
output, carry input to function outputs,
Fig.8 Propagation delays for operands to carry
generate, propagate outputs and function
outputs.
operands to carry generate operands,
propagation outputs and output transition lines.
Fig.9 Propagation delays for operands to carry
output and function outputs.
Fig.10 Propagation delays for operands to carry
output.
Note to AC waveforms
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
APPLICATION INFORMATION
A and B inputs and F outputs
of “181” are not shown
Fig.11 Waveforms showing the input (Ai, Bj) to output
(A=B) propagation delays and output transition
time of the open drain output (A=B).
Fig.12 Application example showing 16-bit ALU
ripple-carry configuration.
1998 Jun 10
15
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
PACKAGE OUTLINES
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
D
M
E
A
2
A
L
A
1
c
w M
e
Z
b
1
(e )
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
min.
max.
max.
1.63
1.14
0.56
0.43
0.36
0.25
31.9
31.5
6.73
6.48
3.51
3.05
8.13
7.62
10.03
7.62
4.70
0.38
3.94
2.54
0.100
7.62
0.25
0.01
2.05
0.064
0.045
0.022
0.017
0.014
0.010
1.256
1.240
0.265
0.255
0.138
0.120
0.32
0.30
0.395
0.300
inches
0.185
0.015
0.155
0.300
0.081
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-03-11
SOT222-1
MS-001AF
1998 Jun 10
16
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
32.0
31.4
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.51
4.0
2.54
0.10
15.24
0.60
0.25
0.01
2.2
0.066
0.051
0.021
0.015
0.013
0.009
1.26
1.24
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.20
0.020
0.16
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-23
SOT101-1
051G02
MO-015AD
1998 Jun 10
17
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1998 Jun 10
18
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Jun 10
19
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 10
20
相关型号：
©2020 ICPDF网 联系我们和版权申明