74HCT191D-T [NXP]
IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, SOT-109, SO-16, Counter;
| 型号： | 74HCT191D-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, SOT-109, SO-16, Counter 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches
“15” in the count-up-mode. The TC output will remain
HIGH until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the
RC output. When TC is HIGH and CE is LOW, the RC
output follows the clock pulse (CP). This feature simplifies
the design of multistage counters as shown in Figs 5
and 6.
FEATURES
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT191 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
The 74HC/HCT191 are asynchronously presettable 4-bit
binary up/down counters. They contain four master/slave
flip-flops with internal gating and steering logic to provide
asynchronous preset and synchronous count-up and
count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
UNIT
SYMBOL
PARAMETER
CONDITIONS
HC
HCT
t
PHL/ tPLH
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V 22
22
ns
fmax
CI
36
36
3.5
33
MHz
pF
3.5
CPD
power dissipation capacitance per package
notes 1 and 2
31
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
PIN DESCRIPTION
PIN NO.
SYMBOL
Q0 to Q3
CE
NAME AND FUNCTION
3, 2, 6, 7
flip-flop outputs
4
count enable input (active LOW)
up/down input
5
U/D
8
GND
PL
ground (0 V)
11
parallel load input (active LOW)
terminal count output
ripple clock output (active LOW)
12
TC
13
RC
14
CP
clock input (LOW-to-HIGH, edge triggered)
data inputs
15, 1, 10, 9
16
D0 to D3
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
INPUTS
CE
OUTPUTS
Qn
PL
U/D
CP
Dn
L
L
X
X
X
X
X
X
L
H
L
H
parallel load
count up
H
H
H
L
H
X
I
I
↑
↑
X
X
X
count up
count down
hold (do nothing)
count down
no change
H
X
TC AND RC FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
OUTPUTS
U/D
CE
CP
Q0
Q1
Q2
Q3
TC
RC
H
L
L
L
H
H
H
H
L
H
H
L
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
H
X
X
L
H
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
I
= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
Fig.5 N-stage ripple counter using ripple clock.
Fig.6 Synchronous n-stage counter using ripple carry/borrow.
Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
Sequence
Load (preset) to binary thirteen;
count up to fourteen, fifteen,
zero, one and two;
inhibit;
count down to one, zero, fifteen,
fourteen and thirteen.
Fig.8 Typical load, count and
inhibit sequence.
Fig.9 Logic diagram.
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
72
26
21
220
44
37
275
55
47
330
66
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.10
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
CP to TC
83
30
24
255
51
43
320
64
54
395
77
65
2.0 Fig.10
4.5
6.0
PHL/ tPLH propagation delay
CP to RC
47
17
14
150
30
26
190
38
33
225
45
38
2.0 Fig.11
4.5
6.0
PHL/ tPLH propagation delay
CE to RC
33
12
10
130
26
22
165
33
28
195
39
33
2.0 Fig.11
4.5
6.0
PHL/ tPLH propagation delay
Dn to Qn
61
22
18
220
44
37
275
55
47
330
66
56
2.0 Fig.12
4.5
6.0
tPHL/ tPLH propagation delay
PL to Qn
61
22
18
220
44
37
275
55
47
330
66
56
2.0 Fig.13
4.5
6.0
t
t
t
PHL/ tPLH propagation delay
U/D to TC
44
16
13
190
38
32
240
48
41
285
57
48
2.0 Fig.14
4.5
6.0
PHL/ tPLH propagation delay
U/D to RC
50
18
14
210
42
36
265
53
45
315
63
54
2.0 Fig.14
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.15
4.5
6.0
tW
clock pulse width
HIGH or LOW
125 28
155
31
26
195
39
33
2.0 Fig.10
4.5
6.0
25
21
10
8
tW
parallel load pulse width 100 22
125
25
21
150
30
26
2.0 Fig.15
4.5
6.0
LOW
20
17
8
6
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
trem
tsu
tsu
tsu
th
removal time
PL to CP
35
7
6
8
3
2
45
9
8
55
11
9
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.15
4.5
6.0
set-up time
U/D to CP
205 50
41
35
255
51
43
310
62
53
2.0 Fig.17
4.5
6.0
18
14
set-up time
Dn to PL
100 19
20
17
125
25
21
150
30
26
2.0 Fig.16
4.5
6.0
7
6
set-up time
CE to CP
140 44
28
24
175
35
30
210
42
36
2.0 Fig.17
4.5
6.0
16
13
hold time
U/D to CP
0
0
0
−39
−14
−11
0
0
0
0
0
0
2.0 Fig.17
4.5
6.0
th
hold time
Dn to PL
0
0
0
−11
−4
−3
0
0
0
0
0
0
2.0 Fig.16
4.5
6.0
th
hold time
CE to CP
0
0
0
−28
−10
−8
0
0
0
0
0
0
2.0 Fig.17
4.5
6.0
fmax
maximum clock pulse
frequency
4.0
20
24
11
33
39
3.2
16
19
2.6
13
15
MHz 2.0 Fig.10
4.5
6.0
December 1990
9
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
0.5
CP
U/D
CE, PL
0.65
1.15
1.5
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
26
32
19
19
22
27
23
24
7
48
51
35
33
44
46
45
45
15
60
64
44
41
55
58
56
56
19
72
77
53
50
66
69
68
68
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.10
4.5 Fig.10
4.5 Fig.11
4.5 Fig.11
4.5 Fig.12
4.5 Fig.13
4.5 Fig.14
4.5 Fig.14
4.5 Fig.15
4.5 Fig.10
4.5 Fig.15
4.5 Fig.15
4.5 Fig.17
4.5 Fig.16
4.5 Fig.17
4.5 Fig.17
4.5 Fig.16
4.5 Fig.17
t
PHL/ tPLH propagation delay
CP to TC
t
PHL/ tPLH propagation delay
CP to RC
tPHL/ tPLH propagation delay
CE to RC
t
t
t
t
t
PHL/ tPLH propagation delay
Dn to Qn
PHL/ tPLH propagation delay
PL to Qn
PHL/ tPLH propagation delay
U/D to TC
PHL/ tPLH propagation delay
U/D to RC
THL/ tTLH output transition time
tW
tW
trem
tsu
tsu
tsu
th
clock pulse width
HIGH or LOW
16
9
20
28
9
24
33
11
62
30
45
0
parallel load pulse width 22
LOW
11
1
removal time
PL to CP
7
set-up time
U/D to CP
41
20
30
0
20
9
51
25
38
0
set-up time
Dn to PL
set-up time
CE to CP
18
−18
−5
−10
33
hold time
U/D to CP
th
hold time
Dn to PL
0
0
0
th
hold time
CE to CP
0
0
0
fmax
maximum clock pulse
frequency
20
16
13
MHz 4.5 Fig.10
December 1990
11
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width and the
maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation
delays.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the input (Dn) to output (Qn) propagation delays.
December 1990
12
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing the input (PL) to output (Qn) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC)
propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output
(Qn) transition times.
December 1990
13
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
14
相关型号：
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IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, Counter
NXP
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