74HCT1G32GV,125 [NXP]
74HC(T)1G32 - 2-input OR gate TSOP 5-Pin;
| 型号： | 74HCT1G32GV,125 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)1G32 - 2-input OR gate TSOP 5-Pin PC 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC1G32; 74HCT1G32
2-input OR gate
Rev. 05 — 14 March 2008
Product data sheet
1. General description
74HC1G32 and 74HCT1G32 are high-speed Si-gate CMOS devices. They provide a
2-input OR function.
The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
The standard output currents are half those of the 74HC32 and 74HCT32.
2. Features
I Symmetrical output impedance
I High noise immunity
I Low power dissipation
I Balanced propagation delays
I SOT353-1 and SOT753 package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC1G32GW
74HCT1G32GW
74HC1G32GV
74HCT1G32GV
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
SC-74A
plastic surface-mounted package; 5 leads
SOT753
4. Marking
Table 2.
Marking codes
Type number
74HC1G32GW
74HCT1G32GW
74HC1G32GV
74HCT1G32GV
Marking code
HG
TG
H32
T32
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
5. Functional diagram
1
1
2
B
A
≥1
Y
4
4
2
mna165
mna164
Fig 1. Logic symbol
Fig 2. IEC logic symbol
B
A
Y
mna166
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74HC1G32
74HCT1G32
1
2
3
5
4
B
A
V
Y
CC
GND
001aaf104
Fig 4. Pin configuration
6.2 Pin description
Table 3.
Pin description
Pin
Symbol
Description
data input B
data input A
B
1
2
3
4
5
A
GND
Y
ground (0 V)
data output Y
supply voltage
VCC
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
2 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Inputs
Output
A
L
B
L
Y
L
L
H
L
H
H
H
H
H
H
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1]
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
±12.5
25
Unit
V
supply voltage
−0.5
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−25
−65
-
-
storage temperature
total power dissipation
+150
200
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC1G32
74HCT1G32
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
2.0
5.0
4.5
5.0
V
V
V
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
ambient temperature
0
-
0
-
Tamb
∆t/∆V
−40
+25
−40
+25
+125 °C
input transition rise
and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
139
-
ns/V
ns/V
ns/V
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
3 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C.
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
74HC1G32
VIH
HIGH-level input
voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
VIL
LOW-level input
voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −2.0 mA; VCC = 4.5 V
IO = −2.6 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
2.0
4.5
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
6.0
4.13
5.63
4.32
5.81
VOL
LOW-level output
voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 2.0 mA; VCC = 4.5 V
IO = 2.6 mA; VCC = 6.0 V
-
-
-
-
-
-
-
0
0.1
0.1
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
20
V
0
V
0
0.15
0.16
-
0.1
V
0.33
0.33
1.0
V
V
II
input leakage current VI = VCC or GND; VCC = 6.0 V
µA
µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
10
V
CI
input capacitance
-
1.5
-
-
-
pF
74HCT1G32
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
VIL
LOW-level input
voltage
0.8
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
4.5
-
-
4.4
3.7
-
-
V
V
IO = −2.0 mA
4.13
4.32
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
0
0.15
-
0.1
0.33
1.0
-
-
-
0.1
0.4
1.0
V
IO = 2.0 mA
V
II
input leakage current VI = VCC or GND; VCC = 5.5 V
µA
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
4 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C.
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
ICC
∆ICC
CI
supply current
VI = VCC or GND; IO = 0 A;
-
-
-
-
10
500
-
-
20
µA
µA
pF
VCC = 5.5 V
additional supply
current
per input; VCC = 4.5 V to 5.5 V;
VI = VCC − 2.1 V; IO = 0 A
-
-
-
850
-
input capacitance
1.5
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; tr = tf ≤ 6.0 ns. All typical values are measured at Tamb = 25 °C. For test circuit see Figure 6
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
74HC1G32
[1]
tpd
propagation delay A and B to Y; see Figure 5
VCC = 2.0 V; CL = 50 pF
-
-
-
-
-
18
8
115
23
-
-
-
-
-
-
135
27
-
ns
ns
ns
ns
pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
8
VCC = 6.0 V; CL = 50 pF
7
20
-
23
-
[2]
[1]
CPD
power dissipation VI = GND to VCC
capacitance
19
74HCT1G32
tpd
propagation delay A and B to Y; see Figure 5
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
-
-
-
10
10
20
24
-
-
-
-
27
-
ns
ns
pF
[2]
CPD
power dissipation VI = GND to VCC − 1.5 V
-
-
capacitance
[1] tpd is the same as tPLH and tPHL
.
[2] CPD is used to determine the dynamic power dissipation PD (µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
5 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
12. Waveforms
V
A, B input
M
t
t
PLH
PHL
V
Y output
M
mna167
Fig 5. The input (A and B) to output (Y) propagation delays
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
T
mna101
Measurement points are given in Table 8. Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Load circuitry for switching times
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
6 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 7. Package outline SOT353-1 (TSSOP5)
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
7 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 8. Package outline SOT753 (SC-74A)
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
8 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
14. Abbreviations
Table 9.
Acronym
DUT
Abbreviations
Description
Device Under Test
TTL
Transistor-Transistor Logic
15. Revision history
Table 10. Revision history
Document ID
Release date
20080314
Data sheet status
Change notice
Supersedes
74HC_HCT1G32_5
Modifications:
Product data sheet
-
74HC_HCT1G32_4
• Pin description of Pin 4 changed from input to output in Table 3.
74HC_HCT1G32_4
74HC_HCT1G32_3
74HC_HCT1G32_2
74HC_HCT1G32
20070514
20020515
20010406
19971216
Product data sheet
-
-
-
-
74HC_HCT1G32_3
74HC_HCT1G32_2
74HC_HCT1G32
-
Product specification
Product specification
Preliminary specification
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
9 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT1G32_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 14 March 2008
10 of 11
74HC1G32; 74HCT1G32
NXP Semiconductors
2-input OR gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 March 2008
Document identifier: 74HC_HCT1G32_5
相关型号：
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