74HCT20NB [NXP]
HCT SERIES, DUAL 4-INPUT NAND GATE, PDIP14;
| 型号： | 74HCT20NB |
| 厂家： | 
NXP |
| 描述： | HCT SERIES, DUAL 4-INPUT NAND GATE, PDIP14 |
| 文件： | 总6页 (文件大小：38K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT20
Dual 4-input NAND gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
13
tPHL/ tPLH
CI
propagation delay nA, nB, nC, nD to nY
input capacitance
CL = 15 pF; VCC = 5 V
8
3.5
22
3.5
17
pF
pF
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
PIN DESCRIPTION
PIN NO.
1, 9
SYMBOL
1A, 2A
1B, 2B
n.c.
NAME AND FUNCTION
data inputs
2, 10
3, 11
4, 12
5, 13
6, 8
data inputs
not connected
data inputs
1C, 2C
1D, 2D
1Y, 2Y
GND
data inputs
data outputs
7
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
Fig.4 Functional diagram.
Fig.5 HC logic diagram (one gate).
FUNCTION TABLE
INPUTS
OUTPUT
nY
nA
nB
nC
nD
L
X
X
X
H
X
L
X
X
H
X
X
L
X
H
X
X
X
L
H
H
H
H
L
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Fig.6 HCT logic diagram (one gate).
December 1990
4
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT VCC WAVEFORMS
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB, nC, nD to nY
28
10
8
90
18
15
115
23
20
135
27
23
ns
ns
2.0
4.5
6.0
Fig.7
Fig.7
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nA, nB, nC, nD
0.3
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
74HCT
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT VCC WAVEFORMS
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB, nC, nD to nY
16
28
35
42
ns
ns
4.5
4.5
Fig.7
Fig.7
t
THL/ tTLH output transition time
7
15
19
22
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the enable input (nA, nB, nC, nD) to output (nY) propagation delays and the output
transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
6
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