74HCT238U [NXP]
IC HCT SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, UUC, WAFER, Decoder/Driver;
| 型号： | 74HCT238U |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, UUC, WAFER, Decoder/Driver |
| 文件： | 总7页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT238
3-to-8 line decoder/demultiplexer
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
provide 8 mutually exclusive active HIGH outputs
FEATURES
(Y0 to Y7).
• Demultiplexing capability
The “238” features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be
LOW unless E1 and E2 are LOW and E3 is HIGH.
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active HIGH mutually exclusive outputs
• Output capability: standard
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
• ICC category: MSI
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “238” is identical to the “138” but has non-inverting
outputs.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A0, A1, A2) and when enabled,
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
An to Yn
CL = 15 pF; VCC = 5 V
14
16
17
3.5
72
18
20
21
3.5
76
ns
ns
ns
pF
pF
E3 to Yn
En to Yn
CI
input capacitance
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
PIN DESCRIPTION
PIN NO.
SYMBOL
A0 to A2
E1, E2
E3
NAME AND FUNCTION
1, 2, 3
address inputs
4, 5
6
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
8
GND
15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7
outputs (active HIGH)
positive supply voltage
16
VCC
Fig.1 Pin configuration.
(a)
Fig.2 Logic symbol.
(b)
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUTS
Y3 Y4
E1
E2
E3
A0
A1
A2
Y0
Y1
Y2
Y5
Y6
Y7
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Yn
47
17
14
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
PHL/ tPLH propagation delay
E3 to Yn
52
19
15
160
32
27
200
40
34
240
48
41
2.0 Fig.6
4.5
6.0
PHL/ tPLH propagation delay
En to Yn
50
18
14
155
31
26
195
39
33
235
47
40
2.0 Fig.7
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Figs 6 and 7
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
An
En
E3
0.70
0.40
1.45
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
propagation delay
An to Yn
21
17
22
18
21
18
7
35
35
37
37
35
35
15
44
44
46
46
44
44
19
53
53
56
56
53
53
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Figs 6 and 7
propagation delay
An to Yn
propagation delay
E3 to Yn
propagation delay
E3 to Yn
propagation delay
En to Yn
propagation delay
En to Yn
t
THL/ tTLH output transition time
December 1990
6
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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