74HCT297D-T [NXP]

IC SPECIALTY LOGIC CIRCUIT, PDSO16, Logic IC:Other;


型号：	74HCT297D-T
厂家：	NXP
描述：	IC SPECIALTY LOGIC CIRCUIT, PDSO16, Logic IC:Other 光电二极管逻辑集成电路
文件：	总12页 (文件大小：101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT297

Digital phase-locked-loop filter

September 1993

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

components. The accuracy of the digital

FEATURES

phase-locked-loop (DPLL) is not affected by V_CCand

temperature variations but depends solely on accuracies

of the K-clock, I/D-clock and loop propagation delays.

• Digital design avoids analog compensation errors

• Easily cascadable for higher order loops

• Useful frequency range:

The phase detector generates an error signal waveform

that, at zero phase error, is a 50% duty factor square wave.

At the limits of linear operation, the phase detector output

will be either HIGH or LOW all of the time depending on the

direction of the phase error (φ_IN− φ_OUT). Within these limits

the phase detector output varies linearly with the input

phase error according to the gain k_d, which is expressed in

terms of phase detector output per cycle or phase error.

The phase detector output can be defined to vary between

± 1 according to the relation:

– DC to 55 MHz typical (K-clock)

– DC to 35 MHz typical (I/D-clock)

• Dynamically variable bandwidth

• Very narrow bandwidth attainable

• Power-on reset

• Output capability: standard/bus driver

• I_CCcategory: MSI

˙˙

% HIGH – % LOW

phase detector output =

GENERAL DESCRIPTION

------------------------------------------------

100

The 74HC/HCT297 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The output of the phase detector will be k_dφ_e, where the

phase error φ_e= φ_IN− φ_OUT

EXCLUSIVE-OR phase detectors (XORPD) and

edge-controlled phase detectors (ECPD) are commonly

used digital types. The ECPD is more complex than the

XORPD logic function but can be described generally as a

circuit that changes states on one of the transitions of its

inputs. The gain (k_d) for an XORPD is 4 because its output

remains HIGH (XORPD_OUT= 1) for a phase error of 1/4

cycle.

Similarly, k_dfor the ECPD is 2 since its output remains

HIGH for a phase error of 1/2 cycle. The type of phase

detector will determine the zero-phase-error point, i.e., the

phase separation of the phase detector inputs for a

φ_edefined to be zero. For the basic DPLL system of

The 74HC/HCT297 are designed to provide a simple,

cost-effective solution to high-accuracy, digital,

phase-locked-loop applications. These devices contain all

the necessary circuits, with the exception of the

divide-by-n counter, to build first order

phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled

(ECPD) phase detectors are provided for maximum

flexibility. The input signals for the EXCLUSIVE-OR phase

detector must have a 50% duty factor to obtain the

maximum lock-range.

Proper partitioning of the loop function, with many of the

building blocks external to the package, makes it easy for

the designer to incorporate ripple cancellation (see Fig.7)

or to cascade to higher order phase-locked-loops.

Fig.6 φ_e= 0 when the phase detector output is a square

wave.

The XORPD inputs are 1/4 cycle out-of-phase for zero

phase error. For the ECPD, φ_e= 0 when the inputs are 1/2

cycle out-of-phase.

The length of the up/down K-counter is digitally

programmable according to the K-counter function table.

With, A, B, C and D all LOW, the K-counter is disabled.

With A HIGH and B, C and D LOW, the K-counter is only

three stages long, which widens the bandwidth or capture

range and shortens the lock time of the loop. When A, B,

C and D are all programmed HIGH, the K-counter

becomes seventeen stages long, which narrows the

bandwidth or capture range and lengthens the lock time.

Real-time control of loop bandwidth by manipulating the A

to D inputs can maximize the overall performance of the

digital phase-locked loop.

The phase detector output controls the up/down input to

the K-counter. The counter is clocked by input frequency

Mf_c, which is a multiple M of the loop centre frequency f_c.

When the K-counter recycles up, it generates a carry

pulse. Recycling while counting down generates a borrow

pulse. If the carry and the borrow outputs are conceptually

combined into one output that is positive for a carry and

negative for a borrow, and if the K-counter is considered as

a frequency divider with the ratio Mf_c/K, the output of the

K-counter will equal the input frequency multiplied by the

division ratio. Thus the output from the K-counter is

(k_dφ_eMf_c) / K.

The “297” can perform the classic first-order

phase-locked-loop function without using analog

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

The carry and borrow pulses go to the

The output of the N-counter (or the output of the

increment/decrement (I/D) circuit which, in the absence of

any carry or borrow pulses has an output that is 1/2 of the

input clock (I/D_CP). The input clock is just a multiple, 2N, of

the loop centre frequency. In response to a carry or borrow

pulse, the I/D circuit will either add or delete a pulse at

I/D_OUT. Thus the output of the I/D circuit will be

Nf_c+ (k_{d e}Mf_c)/2K.

phase-locked-loop) is thus: f_o= f_c+ (k_dφ_eMf_c)/2KN.

If this result is compared to the equation for a first-order

analog phase-locked-loop, the digital equivalent of the

gain of the VCO is just Mf_c/2KN or f_c/K for M = 2N.

Thus the simple first-order phase-locked-loop with an

adjustable K-counter is the equivalent of an analog

phase-locked-loop with a programmable VCO gain.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

_PHL/t_PLH

PARAMETER

CONDITIONS

UNIT

HCT

propagation delay

I/D_CPto I/D_OUT

φA₁, φB to XORPD_OUT

φB, φA₂to ECPD_OUT

maximum clock frequency

K_CP

C_L= 15 pF; V_CC= 5 V

f_max

3.5

MHz

I/D_CP

C_I

input capacitance

C_PD

power dissipation capacitance per package notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

2, 1, 15, 14

A, B, C, D

EN_CTR

K_CP

modulo control inputs

K-counter enable input

K-counter clock input (LOW-to-HIGH, edge-triggered)

I/D_CP

increment/decrement clock input (HIGH-to-LOW, edge-triggered)

down/up control

D/U

I/D_OUT

increment/decrement bus output

ground (0 V)

GND

9, 10, 13

φA₁, φB, φA₂

XORPD_OUT

ECPD_OUT

V_CC

phase inputs

EXCLUSIVE-OR phase detector output

edge-controlled phase detector output

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

Fig.4 Functional diagram.

K-COUNTER (DIGITAL CONTROL) FUNCTION TABLE

EXCLUSIVE-OR PHASE DETECTOR FUNCTION

TABLE

MODULO (K)

φA₁

φB

XORPD_OUT

inhibited

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

EDGE-CONTROLLED PHASE DETECTOR TABLE

φA₂

H or L

φB

ECPD_OUT

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

2¹⁵

2¹⁶

2¹⁷

↓

H or L

↑

H or L

↑

no change

Notes

1. H = HIGH voltage level

L = LOW voltage level

↓ = HIGH-to-LOW transition

↑ = LOW-to-HIGH transition

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

Fig.5 Logic diagram.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

Fig.6 DPLL using EXCLUSIVE-OR phase detection.

Fig.7 DPLL using both phase detectors in a ripple-cancellation scheme.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

Fig.8 Timing diagram: I/D_OUTin-lock condition.

Fig.9 Timing diagram: edge-controlled phase comparator waveforms.

Fig.10 Timing diagram: EXCLUSIVE-OR phase detector waveforms.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard/bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

I/D_CPto I/D_OUT

175

220

265

2.0 Fig.11

4.5

6.0

_PHL/ t_PLHpropagation delay

φA₁, φB

160

200

240

2.0 Fig.12

4.5

6.0

to XORPD_OUT

_PHL/ t_PLHpropagation delay

φB, φA₂

220

275

330

2.0 Fig.13

4.5

6.0

to ECPD_OUT

_THL/ t_TLHoutput transition time:

bus driver output;

2.0 Fig.11

4.5

6.0

I/D_OUT(pin 7)

_THL/ t_TLHoutput transition time:

standard outputs;

110

2.0 Fig.12 and 13

4.5

6.0

XORPD_OUT, ECPD_OUT

(pins 11, 12)

t_W

clock pulse width

K_CP

100

120

2.0 Fig.14

4.5

6.0

t_W

clock pulse width

I/D_CP

100 28

125

150

2.0 Fig.11

4.5

6.0

t_su

set-up time

D/U, EN_CTRto K_CP

120 33

150

180

2.0 Fig.14

4.5

6.0

t_h

hold time

D/U, EN_CTRto K_CP

−19

−7

−6

2.0 Fig.14

4.5

6.0

f_max

maximum clock pulse

frequency K_CP

6.0

4.8

4.0

MHz 2.0 Fig.14

4.5

6.0

f_max

maximum clock pulse

frequency I/D_CP

4.0

3.2

2.6

MHz 2.0 Fig.11

4.5

6.0

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

To determine ∆I_CCper input, multiply this value by the unit

DC CHARACTERISTICS FOR 74HCT

load coefficient shown in the table below.

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard/bus driver

I_CCcategory: MSI

INPUT

UNIT LOAD COEFFICIENT

EN_CTR, D/U

0.3

0.6

1.5

Note to HCT types

A, B, C, D, K_CP,φA₂

I/D_CP, φA₁, φB

The value of additional quiescent supply current (∆I_CC) for

a unit load of 1 is given in the family specifications.

AC CHARACTERISTICS FOR 74HCT

GND = 0 V, t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

I/D_CPto I/D_OUT

4.5 Fig.11

4.5 Fig.12

4.5 Fig.13

4.5 Fig.11

_PHL/ t_PLHpropagation delay

φA₁, φB to XORPD_OUT

_PHL/ t_PLHpropagation delay

φB, φA₂to ECPD_OUT

_THL/ t_TLHoutput transition time

bus driver output

I/D_OUT(pin 7)

t_THL/ t_TLHoutput transition time

standard outputs

4.5 Figs 12 and 13

XORPD_OUT, ECPD_OUT

(pins 11, 12)

t_W

clock pulse width

K_CP

4.5 Fig.14

4.5 Fig.11

4.5 Fig.14

t_W

clock pulse width

I/D_CP

−8

t_su

set-up time

D/U, EN_CTRto K_CP

t_h

hold time

D/U, EN_CTRto K_CP

f_max

maximum clock pulse

frequency K_CP

MHz 4.5 Fig.14

MHz 4.5 Fig.11

maximum clock pulse

frequency I/D_CP

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.11 Waveforms showing the clock (I/D_CP) to output (I/D_OUT) propagation delays, the clock pulse width, output

transition times and maximum clock pulse frequency.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.12 Waveforms showing the phase input (φB, φA₁) to output (XORPD_OUT) propagation delays and output

transition times.

September 1993

Philips Semiconductors

Product speciﬁcation

Digital phase-locked-loop ﬁlter

74HC/HCT297

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.13 Waveforms showing the phase input (φB, φA₂) to output (ECPD_OUT) propagation delays and output

transition times.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.14 Waveforms showing the clock (K_CP) pulse width and the maximum clock pulse frequency, and the input

(D/U, EN_CTR) to clock (K_CP) set-up and hold times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993

74HCT297D-T [NXP]

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