74HCT2G86GD [NXP]
Dual 2-input exclusive-OR gate; 双2输入异或门
| 型号： | 74HCT2G86GD |
| 厂家： | 
NXP |
| 描述： | Dual 2-input exclusive-OR gate |
| 文件： | 总14页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC2G86; 74HCT2G86
Dual 2-input exclusive-OR gate
Rev. 03 — 7 May 2009
Product data sheet
1. General description
The 74HC2G86 and 74HCT2G86 are high-speed Si-gate CMOS devices. They provide
two 2-input exclusive-OR gates.
The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features
I Wide supply voltage range from 2.0 V to 6.0 V
I Symmetrical output impedance
I High noise immunity
I Low power dissipation
I Balanced propagation delays
I Multiple package options
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC2G86DP
74HCT2G86DP
74HC2G86DC
74HCT2G86DC
74HC2G86GD
74HCT2G86GD
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
XSON8U plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
4. Marking
Table 2.
Marking code
Type number
74HC2G86DP
74HCT2G86DP
74HC2G86DC
74HCT2G86DC
74HC2G86GD
74HCT2G86GD
Marking code
H86
T86
H86
T86
H86
T86
5. Functional diagram
= 1
1A
1Y
1B
2A
2Y
= 1
2B
001aah760
001aah761
Fig 1. Logic symbol
Fig 2. IEC logic symbol
B
A
Y
mna040
Fig 3. Logic diagram (one gate)
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
2 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
6. Pinning information
6.1 Pinning
74HC2G86
74HCT2G86
1A
1B
1
2
3
4
8
7
6
5
V
CC
74HC2G86
74HCT2G86
1Y
2B
2A
2Y
1
2
3
4
8
7
6
5
1A
1B
V
CC
1Y
2B
2A
GND
2Y
GND
001aak027
Transparent top view
001aak026
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT996-2 (XSON8U)
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
Pin description
Pin
1, 5
2, 6
4
Description
data input
data input
ground (0 V)
data output
supply voltage
1Y, 2Y
VCC
7, 3
8
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nB
L
nY
L
L
H
L
H
H
L
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
3 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
25
Unit
V
supply voltage
−0.5
[1]
[1]
[1]
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
50
IGND
Tstg
PD
ground current
−50
−65
-
-
storage temperature
dynamic power dissipation
+150
300
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC2G86
74HCT2G86
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
2.0
5.0
4.5
5.0
V
V
V
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
ambient temperature
0
-
+25
-
0
-
+25
-
Tamb
∆t/∆V
−40
−40
+125 °C
input transition rise
and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
-
139
-
ns/V
1.67
-
1.67
-
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC2G86
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
3.15 2.4
4.2 3.2
1.2
-
-
-
1.5
3.15
4.2
-
-
-
1.5
3.15
4.2
-
-
-
V
V
V
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
4 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
0.5
Min
Max
0.5
VIL
LOW-level
VCC = 2.0 V
-
-
-
0.8
0.5
-
-
-
-
-
-
V
V
V
input voltage
VCC = 4.5 V
2.1 1.35
1.35
1.8
1.35
1.8
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4.0 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
4.18 4.32
5.68 5.81
4.13
5.63
VOL
LOW-level
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
V
V
II
input leakage VI = VCC or GND;
current CC = 6.0 V
-
±0.1
1.0
-
µA
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
-
-
10
-
-
-
20
-
µA
V
input
1.5
pF
capacitance
74HCT2G86
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −4.0 mA
4.18 4.32
4.13
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA
0.15 0.26
0.33
±1.0
V
II
input leakage VI = VCC or GND;
current CC = 5.5 V
-
-
-
±0.1
±1.0
µA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
1.0
-
-
10
-
-
20
µA
µA
V
additional
per input;
300
375
410
supply current VCC = 4.5 V to 5.5 V;
VI = VCC − 2.1 V; IO = 0 A
CI
input
-
1.5
-
-
-
-
-
pF
capacitance
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
5 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions
74HC2G86
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[1]
[2]
[3]
tpd
propagation nA, nB to nY; see Figure 6
delay
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
nY; see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
34
11
120
20
-
-
-
150
25
-
-
-
180
36
ns
ns
ns
9.0
17
21
30
tt
transition
time
-
-
18
6
75
15
13
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
20
-
ns
ns
ns
pF
5
CPD
power
per buffer;
-
10
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
74HCT2G86
tpd propagation nA, nB to nY; see Figure 6
[1]
[2]
[3]
delay
VCC = 4.5 V
nY; see Figure 6
VCC = 4.5 V
-
11
19
-
23
-
48
ns
tt
transition
time
-
-
6
9
15
-
-
-
19
-
-
-
22
-
ns
CPD
power
per buffer;
pF
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] tpd is the same as tPLH and tPHL
.
[2] tt is the same as tTLH and tTHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
6 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
12. Waveforms
V
I
nA, nB input
GND
V
M
t
t
PLH
PHL
V
OH
V
Y
V
nY output
M
V
X
V
OL
t
t
TLH
THL
001aak020
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY)
Table 9.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC2G86
0.5VCC
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HCT2G86
1.3 V
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
7 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Test circuit for measuring switching times
Table 10. Test data
Type
Input
Load
CL
S1 position
tPHL, tPLH
open
VI
tr, tf
RL
74HC2G86
GND to VCC
GND to 3 V
≤ 6 ns
≤ 6 ns
50 pF
50 pF
1 kΩ
1 kΩ
74HCT2G86
open
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
8 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 8. Package outline SOT505-2 (TSSOP8)
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
9 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 9. Package outline SOT765-1 (VSSOP8)
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
10 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 10. Package outline SOT996-2 (XSON8U)
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
11 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
20090507
Data sheet status
Change notice
Supersedes
74HC_HCT2G86_3
Modifications:
Product data sheet
-
74HC_HCT2G86_2
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74HC2G86GD and 74HCT2G86GD (XSON8U package)
74HC_HCT2G86_2
74HC_HCT2G86_1
20030728
Product specification
-
74HC_HCT2G86_1
20020717
Product specification
-
-
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
12 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT2G86_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2009
13 of 14
74HC2G86; 74HCT2G86
NXP Semiconductors
Dual 2-input exclusive-OR gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 May 2009
Document identifier: 74HC_HCT2G86_3
相关型号：
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