74HCT40104DB-T [NXP]
IC HCT SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register;
| 型号： | 74HCT40104DB-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register 移位寄存器 |
| 文件： | 总8页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT40104
4-bit bidirectional universal shift
register; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit bidirectional universal shift
register; 3-state
74HC/HCT40104
In the parallel-load mode (S0 and S1 are HIGH), data is
loaded into the associated flip-flop and appears at the
output after the positive transition of the clock input (CP).
FEATURES
• Synchronous parallel or serial operating
• 3-state outputs
During loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the positive
• Output capability: bus driver
• ICC category: MSI
clock edge with serial data entered at the shift-right (DSR
and shift-left (DSL) serial inputs, respectively.
)
GENERAL DESCRIPTION
Clearing the register is accomplished by setting both mode
controls (S0 and S1) LOW and clocking the register. When
the output enable input (OE) is LOW, all outputs assume
the high-impedance OFF-state (Z).
The 74HC/HCT40104 are high-speed Si-gate CMOS
devices and are pin compatible with the “40104” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
APPLICATIONS
The 74HC/HCT40104 are universal shift registers
featuring parallel inputs, parallel outputs, shift-right and
shift-left serial inputs and 3-state outputs allowing the
devices to be used in bus-organized systems.
• Arithmetic unit bus registers
• Serial/parallel conversion
• General-purpose register for bus organized systems
• General-purpose registers
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
13
HCT
15
tPHL/ tPLH
fmax
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
ns
62
3.5
75
57
3.5
75
MHz
pF
CI
CPD
power dissipation capacitance per package notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
3-state output enable input (active HIGH)
serial data shift-right input
parallel data inputs
1
OE
2
DSR
3, 4, 5, 6
D0 to D3
DSL
7
serial data shift-left input
ground (0 V)
8
GND
S0, S1
CP
9, 10
mode control inputs
11
clock input (LOW-to-HIGH, edge-triggered)
3-state parallel outputs
15, 14, 13, 12
16
Q0 to Q3
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
FUNCTION TABLE
INPUTS (OE = HIGH)
OUTPUTS at tn+1
OPE-
RATING
MODES
S1 S0 DSR DSL D0 Q0 Q1 Q2 Q3
to
D3
reset
L
L
X
X
X
L
L
L
L
H
H
L
L
X
X
L
H
X
X
Q1 Q2 Q3
Q1 Q2 Q3
L
H
shift left
L
L
H
H
L
H
X
X
X
X
L
H
Q0 Q1 Q2
Q0 Q1 Q2
shift right
parallel
load
H
H
H
H
X
X
X
X
L
H
L
H
L
H
L
H
L
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
t
n+1 = state after next LOW-to-HIGH transition of CP
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
44
16
13
170
34
29
215
43
37
255
51
43
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
PZH/ tPZL 3-state output enable time
OE to Qn
33
12
10
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
PHZ/ tPLZ 3-state output disable time
OE to Qn
50
18
14
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.6
4.5
6.0
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
set-up time
Dn, DSR, DSL to CP
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
S0, S1 to CP
80
16
14
22
8
6
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
hold time
2
2
2
−8
−3
−2
2
2
2
2
2
2
2.0 Fig.8
4.5
6.0
Dn, DSR, DSL to CP
th
hold time
2
2
2
−14
−5
−4
2
2
2
2
2
2
2.0 Fig.8
4.5
6.0
S0, S1 to CP
fmax
maximum clock pulse
frequency
6.0 19
4.8
24
28
4.0
20
24
MHz 2.0 Fig.6
30
35
56
67
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
D0 to D3
DSR, DSL
CP
S0, S1
OE
0.35
0.35
0.35
0.70
1.40
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
18
12
21
5
34
30
35
12
43
38
44
15
51
45
53
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.8
4.5 Fig.8
4.5 Fig.6
4.5 Fig.6
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
t
t
t
PZH/ tPZL 3-state output enable time
OE to Qn
PHZ/ tPLZ 3-state output disable
time OE to Qn
THL/ tTLH output transition time
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
16
16
20
2
7
20
20
25
2
24
24
30
2
set-up time
Dn, DSR, DSL to CP
8
set-up time
S0, S1 to CP
9
hold time
−2
−5
52
Dn, DSR, DSL to CP
th
hold time
2
2
2
S0, S1 to CP
fmax
maximum clock pulse
frequency
27
22
18
MHz 4.5 Fig.6
December 1990
6
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the set-up and hold times from the Dn, DSR, DSL and Sn inputs to the clock (CP).
December 1990
7
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
8
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