74HCT4017BQ [NXP]
Johnson decade counter with 10 decoded outputs; 10解码输出约翰逊十进制计数器
| 型号： | 74HCT4017BQ |
| 厂家： | 
NXP |
| 描述： | Johnson decade counter with 10 decoded outputs |
| 文件： | 总23页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 03 — 8 January 2008
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4017.
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded active
HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9),
active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous
master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3).
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW)
independent of the clock inputs (CP0 and CP1).
Automatic code correction of the counter is provided by an internal circuit: following any
illegal code the counter returns to a proper counting mode within 11 clock pulses.
2. Features
■ Multiple package options
■ Complies with JEDEC standard no. 7 A
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC4017
74HC4017N
74HC4017D
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC4017DB
74HC4017PW
74HC4017BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
74HCT4017
74HCT4017N
74HCT4017D
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT4017BQ
−40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
4. Functional diagram
CP1
13
CP0
14
5-STAGE JOHNSON COUNTER
MR
15
Q5-9
DECODING AND OUTPUT CIRCUITRY
12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
2
4
7
10
1
5
6
9
11
001aah242
Fig 1. Functional diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
2 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
CTRDIV10/DEC
14
13
15
3
0
1
2
3
4
5
6
7
8
9
CP1
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
3
&
2
CP0
2
14
4
CT = 0
4
7
7
10
1
10
1
5
5
6
15
MR
6
9
9
11
12
11
12
CT≥5
Q5-9
001aah239
001aah240
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D
Q
D
Q
D
Q
D
Q
D
Q
CP1
CP0
MR
FF
1
FF
2
FF
3
FF
4
FF
5
CP Q
RD
CP Q
RD
CP Q
RD
CP Q
RD
CP Q
RD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig 4. Logic diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
3 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
001aah244
Fig 5. Timing diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
4 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
5. Pinning information
5.1 Pinning
74HC4017
74HCT4017
terminal 1
index area
74HC4017
74HCT4017
2
3
4
5
6
7
15
14
13
12
11
10
Q1
Q0
Q2
Q6
Q7
Q3
MR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q5
Q1
V
CC
CP0
CP1
Q5-9
Q9
MR
CP0
CP1
Q5-9
Q9
Q0
Q2
(1)
GND
Q6
Q4
Q7
Q3
Q4
GND
Q8
001aah241
001aah238
Transparent top view
Fig 6. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 7. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
Q[0:9]
GND
Q5-9
CP1
Pin description
Pin
Description
3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
8
ground (0 V)
12
13
14
15
16
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
clock input (LOW-to-HIGH edge-triggered)
master reset input (active HIGH)
supply voltage
CP0
MR
VCC
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
5 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
6. Functional description
Table 3.
MR
Function table[1]
CP0
CP1
Operation
H
X
X
Q0 = Q5-9 = HIGH;
Q1 to Q9 = LOW
L
L
L
L
L
L
H
↑
↓
counter advances
counter advances
no change
L
X
H
↑
L
X
H
↓
no change
no change
L
no change
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
±20
±20
±25
50
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
DIP16 package
+150
Tamb = −40 °C to +125 °C
[2]
[3]
[4]
[5]
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 °C.
[3] Ptot derates linearly with 8 mW/K above 70 °C.
[4] Ptot derates linearly with 5.5 mW/K above 60 °C.
[5] Ptot derates linearly with 4.5 mW/K above 60 °C.
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
6 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
8. Recommended operating conditions
Table 5.
Symbol
74HC4017
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
2.0
5.0
6.0
V
VI
input voltage
0
-
VCC
VCC
625
139
83
V
VO
output voltage
0
-
V
∆t/∆V
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
-
-
ns/V
ns/V
ns/V
°C
-
1.67
VCC = 6.0 V
-
-
-
Tamb
74HCT4017
VCC
ambient temperature
−40
+125
supply voltage
4.5
0
5.0
5.5
V
VI
input voltage
-
VCC
VCC
139
+125
V
VO
output voltage
0
-
V
∆t/∆V
Tamb
input transition rise and fall rate VCC = 4.5 V
ambient temperature
-
1.67
-
ns/V
°C
−40
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC4017
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5 1.2
3.15 2.4
4.2 3.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
VCC = 6.0 V
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.8
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4.0 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
1.9 2.0
4.4 4.5
5.9 6.0
3.98 4.32
5.48 5.81
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
3.84
5.34
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
7 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
V
V
II
input leakage VI = VCC or GND;
current CC = 6.0 V
-
±0.1
8.0
-
µA
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
µA
V
input
3.5
pF
capacitance
74HCT4017
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0 1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
-
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4 4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −4 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA
0.15 0.26
0.33
±1.0
V
II
input leakage VI = VCC or GND;
current CC = 5.5 V
-
±0.1
±1.0
µA
V
ICC
∆ICC
supply current VI = VCC or GND;
CC = 5.5 V; IO = 0 A
-
-
8.0
-
80
-
160
µA
V
additional
per input pin;
supply current VI = VCC − 2.1 V;
other inputs at VCC or GND;
CC = 4.5 V to 5.5 V;
IO = 0 A
V
CP0 input
-
-
-
-
25
40
50
3.5
90
144
180
-
-
-
-
-
113
180
225
-
-
-
-
-
123
196
245
-
µA
µA
µA
pF
CP1 input
MR input
CI
input
capacitance
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
8 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC4017
[1]
tpd
propagation
delay
CP0 to Qn; CP0 to Q5-9;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
-
-
-
63
23
20
230
46
-
-
-
-
290
58
-
-
-
-
345
69
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
18
39
-
49
-
59
ns
CP1 to Qn; CP1 to Q5-9;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
-
-
-
61
22
20
250
50
-
-
-
-
315
63
-
-
-
-
375
75
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
18
43
-
54
-
64
ns
tPHL
HIGH to LOW
propagation
delay
MR to Q[1:9];
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
52
19
15
230
46
-
-
-
290
58
-
-
-
345
69
ns
ns
ns
39
49
59
tPLH
LOW to HIGH
propagation
delay
MR to Q5-9, Q0;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
55
20
16
230
46
-
-
-
290
58
-
-
-
345
69
ns
ns
ns
39
49
59
[2]
tt
transition time
pulse width
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
tW
CP0 and CP1 (HIGH or
LOW); see Figure 9
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
MR (HIGH); see Figure 9
VCC = 2.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
9 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tsu
set-up time
hold time
CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
−8
−3
−2
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
th
CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
17
6
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
5
trec
recovery time
MR to CP0 and
MR to CP1; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
5
5
5
−17
−6
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
−5
fmax
maximum
frequency
CP0 or CP1; see Figure 9
VCC = 2.0 V
6.0
30
-
23
70
77
-
-
-
4.8
24
-
-
-
-
4.0
20
-
-
-
-
MHz
MHz
MHz
VCC = 4.5 V
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
25
-
83
35
-
-
28
-
-
-
24
-
-
-
MHz
pF
[3]
[1]
CPD
power
VI = GND to VCC
VCC = 5 V; fi = 1 MHz
;
dissipation
capacitance
74HCT4017
tpd
propagation
CP0 to Qn; CP0 to Q5-9;
see Figure 10
delay
VCC = 4.5 V
-
-
25
21
46
-
-
-
58
-
-
-
69
-
ns
ns
VCC = 5.0 V;
CL = 15 pF
CP1 to Qn; CP1 to Q5-9;
see Figure 10
VCC = 4.5 V
-
-
25
21
50
-
-
-
63
-
-
-
75
-
ns
ns
VCC = 5.0 V;
CL = 15 pF
tPHL
HIGH to LOW
propagation
delay
MR to Q[1:9];
see Figure 10
VCC = 4.5 V
-
-
22
20
46
46
-
-
58
58
-
-
69
69
ns
ns
tPLH
LOW to HIGH
propagation
delay
MR to Q5-9, Q0;
see Figure 10
VCC = 4.5 V
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
10 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[2]
tt
transition time
pulse width
see Figure 10
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
CP0 and CP1 (HIGH or
LOW); see Figure 9
VCC = 4.5 V
16
16
7
4
-
-
20
20
-
-
24
24
-
-
ns
ns
MR (HIGH); see Figure 9
VCC = 4.5 V
tsu
set-up time
hold time
CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
10
10
5
−3
6
-
-
-
13
13
5
-
-
-
15
15
5
-
-
-
ns
ns
ns
th
CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
trec
recovery time
MR to CP0 and
MR to CP1; see Figure 9
VCC = 4.5 V
−5
fmax
maximum
frequency
CP0 or CP1; see Figure 9
VCC = 4.5 V
30
-
61
67
-
-
24
-
-
-
20
-
-
-
MHz
MHz
VCC = 5.0 V;
CL = 15 pF
[3]
CPD
power
VI = GND to VCC − 1.5 V;
-
36
-
-
-
-
-
pF
dissipation
capacitance
VCC = 5 V; fi = 1 MHz
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
11 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
11. Waveforms
V
I
CP0 input
GND
V
M
t
t
t
t
h
su
h
su
V
I
CP1 input
GND
V
M
001aah245
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0
1/f
max
t
W
V
I
CP0 input
GND
V
V
M
M
1/f
max
V
I
CP1 input
GND
t
W
t
rec
V
I
MR input
GND
V
M
t
W
V
OH
Q1 - Q9
output
V
M
M
V
OL
t
t
PHL
PLH
V
OH
Q0, Q5 - Q9
output
V
V
OL
001aah246
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
12 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
V
I
CP0 input
GND
V
V
M
M
V
I
CP1 input
GND
t
t
t
t
PHL
PLH
PLH
PHL
V
OH
Q1 - Q9
output
V
M
V
OL
V
OH
Q0, Q5 - Q9
output
V
M
V
OL
t
t
TLH
THL
001aah247
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a
HIGH-to-LOW transition.
Fig 10. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition
times
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC4017
0.5 × VCC
1.3 V
0.5 × VCC
1.3 V
74HCT4017
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
13 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Load circuitry for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC4017
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT4017
open
GND
VCC
12. Application information
Some examples of applications for the 74HC4017; 74HCT4017 are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer
Figure 12 shows a technique for extending the number of decoded output states for the
74HC4017; 74HCT4017. Decoded outputs are sequential within each stage and from
stage to stage, with no dead time (except propagation delay).
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
14 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
MR
MR
MR
CP0
CP0
CP0
74HC4017
74HC4017
74HC4017
74HCT4017
CP1
74HCT4017
CP1
74HCT4017
CP1
- - - -
- - - -
- - - - - -
Q1 Q8 Q9
Q0 Q1
Q8 Q9
Q0 Q1
Q8 Q9
9 decoded
outputs
8 decoded
outputs
8 decoded
outputs
clock
first stage
intermediate stages
last stage
001aah248
Fig 12. Counter expansion
Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0
when CP1 is LOW, as this would cause an extra count.
Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one
74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset,
the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output
pulse widths can be enlarged by inserting an RC network at the MR input.
74HC4017
74HCT4017
divide - by 5
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
V
V
CC
CC
MR
CP0
CP1
Q5-9
Q9
fin
divide - by 2
divide - by 6
divide - by 7
divide - by 3
divide - by 10
divide - by 9
divide - by 4
divide - by 8
Q4
Q8
fout
001aah249
Fig 13. Divide-by 2 through divide-by 10
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
15 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 14. Package outline SOT38-4 (DIP16)
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
16 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 15. Package outline SOT109-1 (SO16)
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
17 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 16. Package outline SOT338-1 (SSOP16)
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
18 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 17. Package outline SOT403-1 (TSSOP16)
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
19 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 18. Package outline SOT763-1 (DHVQFN16)
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
20 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date
20080108
Data sheet status
Change notice Supersedes
74HC_HCT4017_CNV_2
74HC_HCT4017_3
Modifications:
Product data sheet
-
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN16 package added.
• Section 7: derating values added for DHVQFN16 package.
• Section 13: outline drawing added for DHVQFN16 package.
74HC_HCT4017_CNV_2
19970829
Product specification
-
-
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
21 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
22 of 23
74HC4017; 74HCT4017
NXP Semiconductors
Johnson decade counter with 10 decoded outputs
18. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 January 2008
Document identifier: 74HC_HCT4017_3
相关型号：
74HCT4017D-Q100
HCT SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
NXP
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