74HCT4024 [NXP]
7-stage binary ripple counter; 7级二进制纹波计数器
| 型号： | 74HCT4024 |
| 厂家： | 
NXP |
| 描述： | 7-stage binary ripple counter |
| 文件： | 总7页 (文件大小：46K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4024
7-stage binary ripple counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
The counter advances on the HIGH-to-LOW transition of
CP.
FEATURES
• Output capability: standard
• ICC category: MSI
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
GENERAL DESCRIPTION
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
APPLICATIONS
The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
outputs (Q0 to Q6).
• Frequency dividing circuits
• Time delay circuits
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
14
HCT
14
tPHL/ tPLH
fmax
propagation delay CP to Q0
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
ns
90
3.5
25
70
3.5
27
MHz
pF
CI
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
2
CP
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel outputs
MR
12, 11, 9, 6, 5, 4, 3 Q0 to Q6
7
GND
n.c.
ground (0 V)
8, 10, 13
14
not connected
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
FUNCTION TABLE
INPUTS
OUTPUTS
Qn
CP
MR
↑
↓
X
L
L
H
no change
count
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +125 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q0
47
17
14
175
35
30
220
44
37
265
53
45
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
tPHL
propagation delay
MR to Q0
63
23
18
200
40
34
250
50
43
300
60
51
2.0 Fig.6
4.5
6.0
t
t
PHL/ tPLH propagation delay
25
9
7
80
16
14
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
Qn to Qn+1
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.6
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
tW
master reset pulse width
HIGH
80
16
14
22
8
6
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
trem
removal time
MR to CP
50
10
9
6
2
2
65
13
11
75
15
13
2.0 Fig.6
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
27
82
98
4.8
24
28
4.0
20
24
MHz 2.0 Fig.6
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP
MR
0.75
0.85
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +125 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q0
17
21
9
35
40
16
15
44
50
20
19
53
60
24
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
tPHL
propagation delay
MR to Q0
t
t
PHL/ tPLH propagation delay
Qn to Qn+1
THL/ tTLH output transition time
7
tW
clock pulse width
HIGH or LOW
16
16
10
30
9
20
20
13
24
24
24
15
20
tW
master reset pulse width
HIGH
6
trem
fmax
removal time
MR to CP
0
maximum clock pulse
frequency
64
MHz 4.5 Fig.6
December 1990
6
Philips Semiconductors
Product specification
7-stage binary ripple counter
74HC/HCT4024
AC WAVEFORMS
Also showing the master reset (MR) pulse width, the
master reset to output (Qn) propagation delays and the
master reset to clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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