74HCT4059D,112 [NXP]
74HC(T)4059 - Programmable divide-by-n counter SOP 24-Pin;
| 型号： | 74HCT4059D,112 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)4059 - Programmable divide-by-n counter SOP 24-Pin 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4059
Programmable divide-by-n counter
1998 Jul 08
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
In the divide-by-n mode, a clock cycle wide pulse is
generated with a frequency rate equal to the input
frequency divided by n.
FEATURES
• Synchronous programmable divide-by-n counter
• Presettable down counter
The function of the mode select and JAM inputs are
illustrated in the following examples. In the divide-by-2
mode, only one flip-flop is needed in the first counting
section. Therefore the last (5th) counting section has three
flip-flops that can be preset to a maximum count of seven
with a place value of thousands. This counting mode is
selected when Ka to Kc are set HIGH. In this case input J1
is used to preset the first counting section and J2 to J4 are
used to preset the last (5th) counting section.
• Fully static operation
• Mode select control of initial decade counting function
(divide-by-10, 8, 5, 4 and 2)
• Master preset initialization
• Latchable output
• Easily cascadable with other counters
• Four operating modes:
timer
divider-by-n
divide-by-10 000
master preset
If the divide-by-10 mode is desired for the first section, Ka
and Kb are set HIGH and Kc is set LOW. The JAM inputs
J1 to J4 are used to preset the first counting section (there
is no last counting section). The intermediate counting
section consists of three cascaded BCD decade
(divide-by-10) counters, presettable by means of the JAM
inputs J5 to J16.
• Output capability: standard
• ICC category: MSI
The preset of the counter to a desired divide-by-n is
achieved as follows:
GENERAL DESCRIPTION
The 74HC/HCT4059 are high-speed Si-gate CMOS
devices and are pin compatible with the “4059” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
n = (MODE(1)) (1 000 x decade 5 preset
+ 100 x decade 4 preset
+ 10 x decade 3 preset
+ 1 x decade 2 preset)
The 74HC/HCT4059 are divide-by-n counters which can
be programmed to divide an input frequency by any
number (n) from 3 to 15 999. There are four operating
modes, timer, divide-by-n, divide-by-10 000 and master
preset, which are defined by the mode select inputs (Ka to
Kc) and the latch enable input (LE) as shown in the
Function table.
+ decade 1 preset
To calculate preset values for any “n” count, divide the “n”
count by the selected mode. The resultant is the
corresponding preset value of the 5th to the 2nd decade
with the remainder being equal to the 1st decade value;
preset value = n/mode.
If n = 8 479, and the selected mode = 5, the preset
value = 8 479/5 = 1 695 with a remainder of 4, thus the
JAM inputs must be set as shown in Table 1.
The complete counter consists of a first counting stage, an
intermediate counting stage and a fifth counting stage. The
first counter stage consists of four independent flip-flops.
Depending on the divide-by-mode, at least one flip-flop is
placed at the input of the intermediate stage (the remaining
flip-flops are placed at the fifth stage with a place value of
thousands). The intermediate stage consists of three
cascaded decade counters, each containing four flip-flops.
To verify the results, use the given equation:
n = 5 (1 000 × 1 + 100 × 6 + 10 × 9 + 1 × 5) + 4
n = 8 479.
If n = 12 382 and the selected mode = 8, the preset
value = 12 382/8 = 1 547 with a remainder of 6, thus the
JAM inputs must be set as shown in Table 2.
All flip-flops can be preset to a desired state by means of
the JAM inputs (J1 to J16), during which the clock input
(CP) will cause all stages to count from n to zero. The
zero-detect circuit will then cause all stages to return to the
JAM count, during which an output pulse is generated. In
the timer mode, after an output pulse is generated, the
output pulse remains HIGH until the latch input (LE) goes
LOW. The counter will advance, even if LE is HIGH and
the output is latched in the HIGH state.
To verify:
n = 8 (1 000 × 1 + 100 × 5 + 10 × 4 + 1 × 7) + 6
n = 12 382.
(1) MODE = first counting section divider
(10, 8, 5, 4 or 2).
1998 Jul 08
2
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
If n = 8 479 and the selected mode = 10, the preset
value = 8 479/10 with a remainder of 9, thus the JAM
inputs must be set as shown in Table 3.
Control inputs Kb and Kc can be used to initiate and lock
the counter in the “master preset” mode. In this condition
the flip-flops in the counter are preset in accordance with
the JAM inputs and the counter remains in that mode as
long as Kb and Kc both remain LOW. The counter begins
to count down from the preset state when a counting mode
other than the “master preset” mode is selected.
Whenever the “master preset” mode is used, control
signals Kb = Kc = LOW must be applied for at least 2 full
clock pulses. After the “master preset” mode inputs have
been changed to one of the counting modes, the next
positive-going clock transition changes an internal flip-flop
so that the count-down begins on the second
To verify:
n = 10 (1 000 × 0 + 100 × 8 + 10 × 4 + 1 × 7) + 9
n = 8 479.
The three decades of the intermediate counting section
can be preset to a binary 15 instead of a BCD 9. In this
case the first cycle of a counter consists of 15 count
pulses, the next cycles consisting of 10 counting pulses.
Thus the place value of the three decades are still 1, 10
and 100. For example, in the divide-by-8 mode, the
number from which the intermediate counting section
begins to count-down can be preset to:
positive-going clock transition. Thus, after a “master
preset” mode, there is always one extra count before the
output goes HIGH. Figure 6 illustrates the operation of the
counter in the divide-by-8 mode starting from the preset
state 3.
3rd decade: 1 500
2nd decade: 150
1st decade:
15
If the “master preset” mode is started two clock cycles or
less before an output pulse, the output pulse will appear at
the correct moment. When the output pulse appears and
the “master preset” mode is not selected, the counter is
preset according to the states of the JAM inputs.
The last counting section can be preset to a maximum of
1, with a place value of 1 000. The first counting section
can be preset to a maximum of 7. To calculate n:
n = 8 (1 000 × 1 + 100 × 15 + 10 × 15 + 1 × 15) + 7
When Ka, Kb, Kc and LE are LOW, the counter operates in
the “preset inhibit” mode, during which the counter divides
at a fixed rate of 10 000, independent of the state of the
JAM inputs. However, the first cycle length after leaving
the “master preset” mode is determined by the JAM inputs.
n = 21 327.
21 327 is the maximum possible count in the divide-by-8
mode. The highest count of the various modes is shown in
the Function table, in the column entitled “binary counter
range”.
When Ka, Kb and Kc are LOW and input LE = HIGH, the
counter operates in the normal divide-by-10 mode,
however, without the latch operation at the output.
The mode select inputs permit, when used with decimal
programming, a non-BCD least significant digit. For
example, the channel spacing in a radio is 12.5 kHz, it may
be convenient to program the counter in decimal steps of
100 kHz subdivided into 8 steps of 12.5 kHz controlled by
the least significant digit. Also frequency synthesizer
channel separations of 10, 12.5, 20, 25 and 50 parts can
be chosen by the mode select inputs. This is called
“Fractional extension”. A similar extension called “Half
channel offset” can be obtained in modes 2, 4, 6 and 8, if
the JAM inputs are switched between zero and 1, 2, 3 and
4 respectfully. This is illustrated in Fig.5.
This device is particularly advantageous in digital
frequency synthesizer circuits (VHF, UHF, FM, AM etc.)
for communication systems, where programmable
divide-by-”n” counters are an integral part of the
synthesizer phase-locked-loop sub-system. The
74HC/HCT4059 can also be used to perform the
synthesizer “fixed divide-by-n” counting function, as well
as general purpose counting for instrumentation functions
such as totalizers, production counters and “time out”
timers.
This feature is used primarily in cases where radio
channels are allocated according to the following formula:
Schmitt-trigger action at the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Channel frequency = channel spacing x (N + 0.5)
N is an integer.
1998 Jul 08
3
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
HC HCT
UNIT
tPHL/ tPLH
propagation delay CP to Q
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V 18
20
40
3.5
32
ns
fmax
CI
40
MHz
pF
3.5
CPD
power dissipation capacitance per package notes 1 and 2
30
pF
Notes
1.
CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
74HC4059N3;
74HCT4059N3
DIP24
DIP24
SO24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
74HC4059N;
74HCT4059N
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
SOT137-1
74HC4059D;
74HCT4059D
plastic small outline package; 24 leads; body width 7.5 mm
1998 Jul 08
4
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
PIN DESCRIPTION
PIN NO.
SYMBOL NAME AND FUNCTION
CP clock input (LOW-to-HIGH, edge-triggered)
LE latch enable (active HIGH)
3, 4, 5, 6, 22, 21, 20, 19, 18, 17, 16, 15, 10, 9, 8, 7 J1 to J16
1
2
programmable JAM inputs (BCD)
ground (0 V)
12
GND
Ka to Kc
Q
14, 13, 11
mode select inputs
23
24
divide-by-n output
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
5
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
APPLICATIONS
• Frequency synthesizer, ideally
suited for use with
PC74HC/HCT4046A,
PC74HC/HCT7046A and
PC74HC/HCT9046A (PLLs)
• Fixed or programmable frequency
division
• “Time out” timer
Fig.4 Functional block diagram.
1998 Jul 08
6
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
FUNCTION TABLE
LATCH
ENABLE
INPUT
MODE
SELECT
INPUTS
FIRST COUNTING
SECTION
LAST COUNTING
SECTION
COUNTER
RANGE
DECADE 1
DECADE 5
OPERATION
MAX
JAM
MAX.
JAM
DIVIDED
BY
BCD
BINARY
MAX.
LE
Ka Kb Kc MODE PRESET INPUTS
STATE USED
PRESET INPUTS
MAX.
STATE
USED
J2J3J4
J3J4
J4
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
2
1
3
4
7
9
1
3
4
7
9
9
J1
8
4
2
2
1
8
4
2
2
1
1
7
15 999 17 331
15 999 18 663
4
J1J2
3
1
1
0
7
3
1
1
0
0
H
L
5
J1J2J3
J1J2J3
J1J2J3J4
J1
9 999 13 329 timer mode
15 999 21 327
L
8
J4
H
H
L
H
H
H
L
10
2
−
9 999 16 659
H
H
H
H
L
J2J3J4
J3J4
J4
15 999 17 331
L
4
J1J2
15 999 18 663
L
H
L
5
J1J2J3
J1J2J3
J1J2J3J4
J1J2J3J4
9 999 13 329
divide-by-n mode
L
L
8
J4
15 999 21 327
9 999 16 659
9 999 16 659
L
H
L
H
H
10
10
−
H
L
−
fixed
−
divide-by-10 000
mode
L
L
H
L
L
L
preset inhibited
master preset
preset inhibited
master preset
10 000
master preset
mode
X
X
−
−
Note
1. It is recommended that the device is in the master preset mode (Kb = Kc = logic 0) in order to correctly initialize the
device prior to start-up. An example of a suitable external circuit is shown in Fig.14.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 1
4
1
1
5
7
7
9
4
4
6
J1
L
J2
J3
H
J4
H
J5
H
J6
L
J7
H
J8
L
J9
H
J10
L
J11
L
J12
H
J13
L
J14
H
J15
J16
L
L
H
Table 2
6
5
J1
L
J2
H
J3
H
J4
H
J5
H
J6
H
J7
H
J8
L
J9
L
J10
L
J11
H
J12
L
J13
H
J14
L
J15
H
J16
L
Table 3
9
8
J1
H
J2
L
J3
L
J4
H
J5
H
J6
H
J7
H
J8
L
J9
L
J10
L
J11
H
J12
L
J13
L
J14
L
J15
L
J16
H
1998 Jul 08
7
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
Fig.5 Half channel offset.
Fig.6 Total count of 3.
1998 Jul 08
8
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
DC CHARACTERISTIC FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
Fig.7
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q
58
21
17
50
18
14
19
7
200
40
250
50
300 ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
60
34
43
51
t
t
PHL/ tPLH propagation delay
LE to Q
175
35
220
44
265 ns
Fig.8
53
30
37
45
THL/ tTLH output transition time
75
95
110 ns
Fig.7
15
19
22
19
ns
6
13
16
tW
clock pulse width
CP
90
18
15
75
15
13
7
115
23
90
95
19
16
3.4
17
20
135
27
Fig.7
6
5
23
trem
removal time
Kb, Kc to CP
19
7
110
22
ns
Fig.9; note 1
Fig.7
6
19
fmax
maximum clock pulse
frequency
4.2 12
2.8
14
MHz 2.0
21
25
36
43
4.5
6.0
17
Note
1. From master preset mode to any other mode.
1998 Jul 08
9
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP
LE
Jn
0.65
0.65
0.50
1.00
1.50
0.85
Ka
Kb
Kc
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q
24
24
7
46
46
15
58
58
19
69
69
22
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
Fig.7
t
PHL/ tPLH propagation delay
LE to Q
Fig.8
tTHL/ tTLH output transition time
Fig.7
tW
clock pulse width
CP
20
15
21
7
25
9
30
22
14
Fig.7
trem
fmax
removal time
Kb, Kc to CP
7
Fig.9; note 1
Fig.7
maximum clock pulse
frequency
36
17
MHz 4.5
Note
1. From master preset mode to any other mode.
1998 Jul 08
10
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
AC WAVEFORMS
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (CP) to output (Q) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the LE input to Q output propagation delay.
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the Kb or Kc removal times, when the operating mode is switched from master preset
to any other mode.
1998 Jul 08
11
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
APPLICATION INFORMATION
Fig.10 Example showing the application of the PC74HC/HCT4059 in a phase-locked-loop (PLL) for a FM band
synthesizer.
Calculating the minimum and maximum divide-by-n
values:
Figure 11 shows a BCD switch compatible arrangement
suitable for divide-by-5 and divide-by-8 modes, which can
be adapted (with minimal changes) to the other
Output frequency range = 87.6 to 103.8 MHz
(CCIR band 2)
divide-by-modes. In order to be able to preset to any
number from 3 to 256 000, while preserving the BCD
switch compatible character of the JAM inputs, a rather
complex cascading scheme is necessary because the
“4059” can never be preset to count less than 3. Logic
circuitry is required to detect a condition where one of the
numbers to be preset in the “4059” is < 3. In order to
simplify the detection logic, only that condition is detected
where the JAM inputs to terminals 6, 7 and 9 would be
LOW during one count. If such a condition is detected, and
if at least 1 is expected to be jammed into the MSB
counter, the detection logic removes one from the number
to be jammed into the MSB counter (with a place value of
2 000 times the divide-by-mode) and jams the same 2 000
into the “4059” by forcing pins 6, 7 and 9 HIGH.
Channel spacing frequency (fc) = 300 kHz
Division factor prescaler (k) = 10
fc
300
---------
10
Reference frequency (fr) =
=
= 30 kHz
---
k
103.8 MHz
----------------------------
300 kHz
Maximum divide-by-n value =
Minimum divide-by-n value =
= 346
87.6 MHz
= 292
-------------------------
300 kHz
3 MHz
Fixed divide-by-n value =
= 100
------------------
30 kHz
The general circuit in Fig.11 can be simplified considerably
if the range of the cascaded counters do not start at a very
low value.
Application of the “4059” as divide-by-n counter allows
programming of the channel spacing (shown in equations
as 300 kHz). A channel in the CCIR band 2 is selected by
the divide-by-n counter as follows:
Figure 12 shows an arrangement in the divide-by-4 mode,
where the counting range extends in a BCD switch
compatible manner from 99 003 to 114 999.
channel = n − 290
1998 Jul 08
12
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
The arrangement shown in Fig.12 is easy to follow; once
during every cycle the programmed digits are jammed in
(15 616 in this example) and then a round number of
11 000 is jammed in, nine times in succession, by forcing
the JAM inputs via AND/OR gates.
In Fig.13 the divide-by-n sub-system is preset once to a
number which represents the least significant digits of the
divide-by number (15 690 in the example shown in Fig.13).
The sub-system is then preset twice to a round number
(8 000 in the example shown in Fig.13) and multiplied by
the number of the divide-by mode (2 in the example shown
in Fig.13).
Numbers larger than the extended counter range can also
be produced by cascading the PC74HC/HCT4059 with
some other counting devices. Figure 13 shows such an
arrangement where only one fixed divide-by number is
desired. The dual flip-flop wired to produce a divide-by-3
count can be replaced by other counters such as the “190”,
“191”, “192”, “193”, “4017”, “4510” and “4516”.
To verify:
15 690 + 2 × 8 000 × 2 = 47 690.
It is important that the second counting device has an
output that is HIGH or LOW during only one of its counting
states.
1998 Jul 08
13
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
Each AND gate is 1/4 of PC74HC/HCT08.
Each OR gate is 1/3 of PC74HC/HCT4075.
Each NOR gate is 1/2 of PC74HC/HCT4002.
Each inverter is 1/6 of PC74HC/HCT04.
Fig.11 BCD switch compatible divide-by-n system suitable for divide-by-5 and divide-by-8 mode. Divides by any
number from 3 to 256 000.
1998 Jul 08
14
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
Fig.12 Dividing-by any number from 99 003 to 114 999 (in this example n = 114 616).
Fig.13 Division by 47 690 in divide-by-2 mode.
1
(1)
RC ≥ -------------------------------------
0.2 × fCP (Hz)
(2) It is assumed that the fCP starts directly after the power-on. Any
additional delay in starting fCP must be added to the RC time.
Fig.14 External circuit for master preset at start-up.
1998 Jul 08
15
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
PACKAGE OUTLINES
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
D
M
E
A
2
A
L
A
1
c
w M
e
Z
b
1
(e )
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
min.
max.
max.
1.63
1.14
0.56
0.43
0.36
0.25
31.9
31.5
6.73
6.48
3.51
3.05
8.13
7.62
10.03
7.62
4.70
0.38
3.94
2.54
0.100
7.62
0.25
0.01
2.05
0.064
0.045
0.022
0.017
0.014
0.010
1.256
1.240
0.265
0.255
0.138
0.120
0.32
0.30
0.395
0.300
inches
0.185
0.015
0.155
0.300
0.081
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-03-11
SOT222-1
MS-001AF
1998 Jul 08
16
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
32.0
31.4
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.51
4.0
2.54
0.10
15.24
0.60
0.25
0.01
2.2
0.066
0.051
0.021
0.015
0.013
0.009
1.26
1.24
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.20
0.020
0.16
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-23
SOT101-1
051G02
MO-015AD
1998 Jul 08
17
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1998 Jul 08
18
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Jul 08
19
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jul 08
20
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