74HCT4066 [NXP]
Quad bilateral switches; 四双边开关
| 型号： | 74HCT4066 |
| 厂家： | 
NXP |
| 描述： | Quad bilateral switches |
| 文件： | 总24页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT4066
Quad bilateral switches
1998 Nov 10
Product specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
The 74HC/HCT4066 have four independent analog
switches. Each switch has two input/output terminals (nY,
nZ) and an active HIGH enable input (nE). When nE is
LOW the belonging analog switch is turned off.
FEATURES
• Very low “ON” resistance:
50 Ω (typ.) at VCC = 4.5 V
45 Ω (typ.) at VCC = 6.0 V
35 Ω (typ.) at VCC = 9.0 V
The “4066” is pin compatible with the “4016” but exhibits a
much lower “ON” resistance. In addition, the “ON”
resistance is relatively constant over the full input signal
range.
• Output capability: non-standard
• ICC category: SSI.
GENERAL DESCRIPTION
The 74HC/HCT4066 are high-speed Si-gate CMOS
devices and are pin compatible with the “4066” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
turn-on time nE to Vos
CONDITIONS
UNIT
ns
HC
HCT
t
PZH/ tPZL
PHZ/ tPLZ
CL = 15 pF; RL = 1 kΩ; VCC = 5 V 11
12
16
3.5
12
8
t
turn-off time nE to Vos
input capacitance
13
ns
pF
pF
pF
CI
3.5
CPD
CS
power dissipation capacitance per switch notes 1 and 2
max. switch capacitance
11
8
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
a) PD = CPD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:
b) fi = input frequency in MHz
c) fo = output frequency in MHz
d) ∑ {(CL + CS) × VCC2 × fo} = sum of outputs
e) CL = output load capacitance in pF
f) CS = maximum switch capacitance in pF
g) VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Nov 10
2
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
74HC4066
74HC4066
74HC4066
74HC4066
74HCT4066
74HCT4066
74HCT4066
74HCT4066
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
SSOP14
TSSOP14
DIP14
plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
SOT108-1
SOT337-1
SO14
plastic small outline package; 14 leads; body width 3.9 mm
plastic shrink small outline package; 14 leads; body width 5.3 mm
SSOP14
TSSOP14
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 4, 8, 11
2, 3, 9, 10
7
1Y to 4Y
1Z to 4Z
GND
independent inputs/outputs
independent inputs/outputs
ground (0 V)
13, 5, 6, 12
14
1E to 4E
VCC
enable inputs (active HIGH)
positive supply voltage
handbook, halfpage
handbook, halfpage
1Y
1Z
1
2
3
4
1Y
1Z
1
2
14
13
12
11
10
9
V
CC
13
5
1E
2E
3E
4E
1E
4E
4Y
4Z
3Z
3Y
2Y
2Z
4
3
2Z
2Y
4066
3Y
3Z
8
9
6
5
6
7
2E
3E
4Y
4Z
11
10
12
8
GND
MGR254
MGR253
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1998 Nov 10
3
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
1
2
3
handbook, halfpage
1
2
3
handbook, halfpage
1
1
1
1
1
13 #
13 #
4
X1
4
1
5
#
5
#
#
X1
8
9
8
6
9
6
#
1
11
10
X1
12 #
11
10
1
MGR255
12 #
X1
MGR256
a.
b.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUT NE
SWITCH
L
off
on
H
Note
1. H = HIGH voltage level; L = LOW voltage level.
13
1
5
4
6
8
12 11
handbook, halfpage
1E 1Y 2E 2Y 3E 3Y 4E 4Y
nY
handbook, halfpage
1Z
2
2Z
3
3Z
9
4Z
10
nE
MGR257
V
V
CC
CC
nZ
GND
MGR258
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
1998 Nov 10
4
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND
(GND = 0 V)
SYMBOL
VCC
PARAMETER
DC supply voltage
MIN. MAX. UNIT
CONDITIONS
−0.5 +11.0
V
±IIK
DC digital input diode current
DC switch diode current
DC switch current
20
20
25
50
mA
mA
mA
mA
for VI < − 0.5 V or VI > VCC + 0.5 V
for VS < − 0.5 V or VS > VCC + 0.5 V
for −0.5 V < VS < VCC + 0.5 V
±ISK
±IIS
±ICC;
DC VCC or GND current
±IGND
Tstg
Ptot
storage temperature range
−65 +150 °C
power dissipation per package
for temperature range: −40 to +125 °C
74HC/HCT
plastic DIL
750
500
100
mW
above +70 °C: derate linearly with 12 mW/K
above +70 °C: derate linearly with 8 mW/K
plastic mini-pack (SO)
power dissipation per switch
mW
mW
PS
Note
1. To avoid drawing VCC current out of terminal nZ, when switch current flows in terminal nY, the voltage drop across
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow
out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ
may not exceed VCC or GND.
RECOMMENDED OPERATING CONDITIONS
74HC
74HCT
SYMBOL
PARAMETER
UNIT
CONDITIONS
min. typ. max. min. typ. max.
VCC
VI
DC supply voltage
2.0
5.0 10.0
VCC
4.5
5.0 5.5
VCC
V
DC input voltage range
DC switch voltage range
GND
GND
−40
GND
GND
−40
V
VS
VCC
VCC
V
Tamb
operating ambient
temperature range
+85
+85
°C
see DC and AC
CHARACTERISTICS
Tamb
tr, tf
operating ambient
temperature range
−40
+125 −40
+125 °C
6.0 500 ns
input rise and fall times
6.0 1000
500
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
400
250
1998 Nov 10
5
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HC/HCT
For 74HC: VCC = 2.0, 4.5, 6.0 and 9.0 V; For 74HCT: VCC = 4.5 V
T
amb (°C)
TEST CONDITIONS
74HC/HCT
SYMBOL
PARAMETER
UNIT
VCC IS
(V) (µA)
+25
−40 to +85 −40 to +125
VIS
VI
min. typ. max. min. max. min. max.
RON
ON-resistance (peak)
−
−
−
−
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
2.0 100 VCC VIH
to
or
54 95
42 84
32 70
118
105
88
−
142
126
105
−
4.5 1000
6.0 1000
9.0 1000
GND VIL
RON
ON-resistance (rail)
ON-resistance (rail)
80
−
2.0 100 GND VIH
or
VIL
35 75
27 65
20 55
95
82
70
−
115
100
85
4.5 1000
6.0 1000
9.0 1000
RON
100
−
−
2.0 100 VCC VIH
or
VIL
42 80
106
94
78
128
113
95
4.5 1000
35 75
6.0 1000
27 60
9.0 1000
∆RON
maximum variation of
ON-resistance between
any two channels
−
5
4
3
2.0
4.5
6.0
9.0
VCC VIH
to or
GND VIL
Note
1. At supply voltages approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
1998 Nov 10
6
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
d
HIGH
(from enable inputs)
V
nY
nZ
I
V
= 0 to V
− GND
CC
is
is
GND
MGR259
Fig.6 Test circuit for measuring ON-resistance (RON).
LOW
(from enable inputs)
nY
nZ
V
= GND or V
CC
V = V
I
or GND
A
A
O
CC
GND
MGR260
Fig.7 Test circuit for measuring OFF-state current.
HIGH
(from enable inputs)
nY
nZ
V
(open circuit)
V = V
I
or GND
A
A
O
CC
GND
MGR261
Fig.8 Test circuit for measuring ON-state current.
7
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
MGR262
60
handbook, halfpage
R
ON
(Ω)
V
= 4.5 V
CC
50
6 V
40
30
20
9 V
10
0
1.8
3.6
5.4
7.2
9
V
(V)
is
Fig.9 Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis = 0 to VCC
.
1998 Nov 10
8
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HC
Voltage are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VI
OTHER
−40 to
+125
VCC
(V)
+25
−40 to +85
min. typ. max. min. max. min. max
VIH
HIGH-level input 1.5
voltage
1.2
1.5
3.15
4.2
6.3
1.5
3.15
4.2
6.3
V
2.0
4.5
6.0
9.0
2.0
4.5
6.0
9.0
3.15 2.4
4.2
6.3
3.2
4.7
VIL
LOW-level input
voltage
0.8 0.50
2.1 1.35
2.8 1.80
4.3 2.70
0.1
0.50
1.35
1.80
2.70
1.0
0.50
1.35
1.80
2.70
1.0
V
±II
input leakage
current
µA
µA
6.0 VCC
or
GND
0.2
2.0
2.0
10.0
±IS
analog switch
OFF-state
current per
channel
0.1
0.1
1.0
1.0
1.0
1.0
10.0 VIH
VS = VCC − GND
(see Fig.7)
or
VIL
±IS
analog switch
µA
10.0 VIH
VS = VCC − GND
ON-state current
or
(see Fig.8)
VIL
ICC
quiescent
supply current
2.0
4.0
20.0
40.0
40.0 µA
6.0 VCC Vis = GND or
or VCC
;
80.0
10.0
GND Vos = VCC or
GND
1998 Nov 10
9
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
OTHER
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
t
PHL/tPLH propagation delay
8
60
12
10
8
75
15
13
10
125
25
21
16
190
38
33
16
90
18
15
12
150
30
26
20
225
45
38
20
ns
2.0 RL = ∞;
Vis to Vos
CL = 50 pF
(see Fig.18)
6.0
3
4.5
2
2
9.0
tPZH/tPZL
turn-on time
nE to Vos
36
13
10
8
100
20
17
13
150
30
26
24
ns
ns
2.0 RL = 1 kΩ;
CL = 50 pF
(see Figs 19
and 20)
4.5
6.0
9.0
tPHZ/tPLZ
turn-off time
nE to Vos
44
16
13
16
2.0 RL = 1 kΩ;
CL = 50 pF
(see Figs 19
and 20)
4.5
6.0
9.0
1998 Nov 10
10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
UNIT
VCC
(V)
−40 to +85 −40 to +125
VI
OTHER
min. typ. max. min. max. min. max.
VIH
VIL
±II
HIGH-level
input voltage
2.0 1.6
1.2
2.0
2.0
V
4.5
to
5.5
LOW-level
input voltage
0.8
0.1
0.1
0.8
1.0
1.0
0.8
1.0
1.0
V
4.5
to
5.5
input leakage
current
µA
µA
5.5
VCC
or
GND
±IS
analog switch
OFF-state
current per
channel
5.5
VIH
or
VIL
VS = VCC − GND
(see Fig.7)
±IS
analog switch
ON-state
current
0.1
2.0
1.0
1.0
µA
5.5
VIH
or
VIL
VS = VCC − GND
(see Fig.8)
ICC
quiescent
supply current
20.0
450
40.0 µA
4.5
to
5.5
VCC
or
Vis = GND or
VCC;Vos = VCC or
GND GND
CC − other inputs at
2.1 V VCC or GND
∆ICC
additional
quiescent
100 360
490
µA
4.5
to
V
supply current
per input pin
for unit load
coefficient is 1
(note 1)
5.5
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input,
multiply this value by the unit load coefficient shown in the table below.
Table 1
INPUT
UNIT LOAD COEFFICIENT
nE
1.00
1998 Nov 10
11
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns
Tamb (°C)
TEST CONDITIONS
OTHER
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/tPLH propagation
3
12
24
35
15
30
44
18
36
53
ns
ns
ns
4.5 RL = ∞; CL = 50 pF
delay Vis to Vos
(see Fig.18)
t
PZH/tPZL turn-on time
nE to Vos
12
20
4.5 RL = 1 kΩ; CL = 50 pF
(see Figs 19 and 20)
tPHZ/tPLZ turn-off time
nE to Vos
4.5 RL = 1 kΩ; CL = 50 pF
(see Figs 19 and 20)
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT
Recommended conditions and typical values GND = 0 V; tr = tf = 6 ns
VCC
(V)
VIS(p−p)
(V)
SYMBOL
PARAMETER
TYP. UNIT
CONDITIONS
sine wave distortion f = 1 kHz
0.04
0.02
0.12
0.06
%
4.5
4.0
8.0
4.0
8.0
RL = 10 kΩ; CL = 50 pF
(see Fig.16)
%
9.0
4.5
9.0
4.5
9.0
4.5
9.0
4.5
9.0
sine wave distortion f = 10 kHz
%
RL = 10 kΩ; CL = 50 pF
(see Fig.16)
%
switch “OFF” signal feed-through −50
−50
dB
dB
dB
dB
mV
mV
note 3
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (see Figs 10 and 17)
crosstalk between any two
switches
−60
−60
note 3
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (see Fig.12)
V(p−p)
crosstalk voltage between enable 110
or address input to any switch
(peak-to-peak value)
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (nE, square wave
between VCC and GND,
tr = tf = 6 ns) (see Fig.14)
220
fmax
minimum frequency response
(−3 dB)
180
200
8
MHz
MHz
pF
4.5
9.0
note 4
RL = 50 Ω; CL = 10 pF
(see Figs 11 and 15)
CS
maximum switch capacitance
Notes
1. Vis is the input voltage at nY or nZ terminal, whichever is assigned as an input.
2. Vos is the output voltage at nY or nZ terminal, whichever is assigned as an output.
3. Adjust input voltage Vis is 0 dBM level (0 dBM = 1 mW into 600 Ω).
4. Adjust input voltage Vis is 0 dBM level at Vos for 1 MHz (0 dBM = 1 mW into 50 Ω).
1998 Nov 10
12
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
MGR263
0
(dB)
−20
−40
−60
−80
−100
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.10 Typical switch “OFF” signal feed-through as a function of frequency.
MGR264
5
(dB)
0
−5
10
2
3
4
5
6
10
10
10
10
10
f (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.11 Typical frequency response.
13
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
V
CC
2R
L
0.1 µF
nY/nZ
nZ/nY
V
i
R
L
2R
C
L
L
channel
ON
GND
MGM265
Fig.12 Test circuit for measuring crosstalk between any two switches; channel ON condition.
V
V
CC
2R
CC
2R
L
L
nY/nZ
nZ/nY
V
os
2R
2R
C
dB
L
L
L
channel
OFF
GND
MGR266
Fig.13 Test circuit for measuring crosstalk between any two switches; channel OFF condition.
V
V
L
The crosstalk is defined as follows
(oscilloscope output):
nE
CC
2R
CC
V
CC
GND
2R
L
L
page
nY/nZ
nZ/nY
V
D.U.T.
os
V(p-p)
2R
2R
C
L
oscilloscope
L
MGR267
GND
MGR268
Fig.14 Test circuit for measuring crosstalk between control and any switch.
14
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
V
CC
2R
L
0.1 µF
nY/nZ
nZ/nY
V
V
os
is
sine-wave
2R
C
dB
L
L
channel
ON
GND
MGR269
Adjust input voltage to obtain 0 dBM at Vos when fin = 1 MHz. After set-up frequency of fin is increased to obtain a reading of −3 dB at Vos
.
Fig.15 Test circuit for measuring minimum frequency response.
V
CC
2R
L
10 µF
nY/nZ
nZ/nY
V
= 1 kHz
V
os
f
is
in
sine-wave
DISTORTION
METER
2R
C
L
L
channel
ON
GND
MGR270
Fig.16 Test circuit for measuring sine wave distortion.
V
CC
2R
L
0.1 µF
nY/nZ
nZ/nY
V
V
os
is
2R
C
dB
L
L
channel
OFF
GND
MGR271
Fig.17 Test circuit for measuring switch “OFF” signal feed-through.
15
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC WAVEFORMS
t
t
f
r
V
CC
90%
50%
V
is
10%
GND
V
50%
os
t
t
PHL
PLH
MGR272
(1) HC: VM = 50%; VI = GND to VCC; HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
t
t
r
f
90 %
(1)
nE INPUT
V
M
10 %
t
t
PZL
PLZ
OUTPUT
LOW - to - OFF
OFF - to - LOW
50 %
10 %
t
t
PHZ
PZH
90 %
OUTPUT
HIGH - to - OFF
OFF - to - HIGH
50 %
outputs
enabled
outputs
disabled
outputs
enabled
MGA846
Fig.19 Waveforms showing the turn-on and turn-off times.
TEST CIRCUIT AND WAVEFORMS
V
V
V
CC
CC is
switch
V
V
O
R
I
L
PULSE
GENERATOR
D.U.T.
open
C
R
L
T
GND
MGR273
Fig.20 Test circuit for measuring AC performance.
16
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
Table 2 Conditions
TEST
SWITCH
GND
VCC
VIS
VCC
tPZH
tPZL
GND
VCC
tPHZ
GND
VCC
tPLZ
GND
pulse
others
open
Table 3 Definitions for Figs 20 and 21:
SYMBOL
DEFINITION
CL
RT
tr
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values)
termination resistance should be equal to the output impedance ZO of the pulse generator
tf = 6 ns, when measuring fmax, there is no constraint on tr, tf with 50% duty factor
t
W
AMPLITUDE
90%
NEGATIVE
INPUT PULSE
V
M
10%
0 V
t
t
(t )
f
t
t
(t )
r
THL
TLH
TLH
THL
(t )
r
(t )
f
AMPLITUDE
90%
M
POSITIVE
INPUT PULSE
V
10%
0 V
t
MGR274
W
Fig.21 Input pulse definitions.
Table 4
FAMILY
tr; tf
AMPLITUDE
VM
fmax
PULSE WIDTH
;
OTHER
74HC
VCC
50%
< 2 ns
6 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
1998 Nov 10
17
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
PACKAGE OUTLINES
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT27-1
050G04
MO-001AA
1998 Nov 10
18
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.050
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT108-1
076E06S
MS-012AB
1998 Nov 10
19
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
96-01-18
SOT337-1
MO-150AB
1998 Nov 10
20
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.10
0.25
0.65
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT402-1
MO-153
1998 Nov 10
21
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1998 Nov 10
22
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
HLQFP, HSQFP, HSOP, SMS
PLCC(4), SO
not suitable(3)
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
suitable
not recommended(4)(5)
LQFP, QFP, TQFP
SQFP
not suitable
not recommended(6)
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Nov 10
23
Philips Semiconductors – a worldwide company
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Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
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Philippines: Philips Semiconductors Philippines Inc.,
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245106/00/03/pp24
Date of release: 1998 Nov 10
Document order number: 9397 750 04779
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