74HCT6323AD [NXP]
Programmable ripple counter with oscillator; 3-state; 与振荡器的可编程脉冲计数器;三态
| 型号： | 74HCT6323AD |
| 厂家： | 
NXP |
| 描述： | Programmable ripple counter with oscillator; 3-state |
| 文件： | 总15页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT6323A
Programmable ripple counter with
oscillator; 3-state
September 1993
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
capacitors minimize external
component count for third overtone
crystal applications.
and sets the output buffer in the
3-state condition. MR can be left
floating since an internal pull-up
resistor will make the MR inactive. In
the HCT version, the MR input and
the two mode select pins S1 and S2
are TTL compatible, but the X1 input
has CMOS input switching levels and
may be driven by a TTL output using
FEATURES
• 8-pin space saving package
• Programmable 3-stage ripple
counter
The oscillator may be replaced by an
external clock signal at input X1. In
this event the other oscillator pin (X2)
must be floating. The counter
advances on the negative-going
transition of X1. A LOW level on MR
resets the counter, stops the oscillator
• Suitable for over-tone crystal
application up to 50 MHz
(VCC = 5 V ± 10%)
• 3-state output buffer
a pull-up resistor connected to VCC
.
• Two internal capacitors
• Recommended operating range for
use with third overtone crystals
3 to 6 V
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
• Oscillator stop function (MR)
TYP.
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
• Output capability:
bus driver → (15 LSTTL)
HC
17
HCT
17
tPHL/tPLH
propagation delay
X1 to OUT
CL = 15 pF;
CC = 5 V
• ICC category: MSI.
V
(S1 = S2 = LOW)
APPLICATIONS
fmax
CI
maximum clock
frequency
90
90
MHz
pF
• Control counters
• Timers
input capacitance
except X1 and X2
3.5
3.5
• Frequency dividers
• Time-delay circuits
CPD
power dissipation
capacitance per
package
+1; notes 1 and 2 54
+2; notes 1 and 2 42
+4; notes 1 and 2 36
+8; notes 1 and 2 33
54
42
36
33
pF
pF
pF
pF
• CIO (Compact Integrated
Oscillator)
• Third-overtone crystal operation.
Notes
GENERAL DESCRIPTION
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC
)
The HC/HCT6323A are high-speed
Si-gate CMOS devices.
where:
They are specified in compliance with
JEDEC standard no. 7A.
fi = input frequency in MHz; fo = output frequency in MHz.
VCC = supply voltage in V; CL = output load capacitance in pF.
Ipull-up = pull-up currents in µA.
The HC/HCT6323A are oscillators
designed for quartz crystal combined
with a programmable 3-state counter,
a 3-state output buffer and an
2. For HC and HCT an external clock is applied to X1 with:
tr = tf ≤ 6 ns, Vi is GND to VCC, MR = HIGH
overriding asynchronous master
reset (MR). With the two select inputs
S1 and S2 the counter can be
switched in the divide-by-1, 2, 4 or 8
mode. If left floating the clock is
divided by 8. The oscillator is
designed to operate either in the
fundamental or third overtone mode
depending on the crystal and external
components applied. On-chip
Ipull-up is the summation of −II (µA) of S1 and S2 inputs at the LOW state.
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
74HC/HCT6323AD
8
SO
plastic
SOT96
September 1993
2
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
PINNING
FUNCTION TABLE
SYMBOL
OUT
PIN
1
DESCRIPTION
counter output
INPUTS
OUTPUTS
S1
0
S2
0
OUT
fi
S1 - S2
3, 2
mode select inputs for divide
by 1, 2, 4 or 8
0
1
fi/2
fi/4
fi/8
GND
MR
X2
4
5
6
7
8
ground (0 V)
1
0
master reset (active LOW)
oscillator pin
1
1
X1
clock input/oscillator pin
positive supply
VCC
6
handbook, halfpage
handbook, halfpage
V
X2
OUT
1
2
3
4
8
7
6
5
CC
X1
7
CP
X1
S2
S1
5
6323A
MR
C
D
X2
3
2
S1
GND
MR
S2
OUT
1
MBA343
MBA344
Fig.1 Pin configuration.
Fig.2 IEC logic symbol.
6
X2
X1
7
3 - STAGE BINARY COUNTER
AND DECODER
CP
C
D
5
MR
S1 S2
OUT
MBA350
3
2
1
Fig.3 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
X2
X1
CP
FF
Q
CP
FF
Q
CP
FF
Q
7 pF
7 pF
(1)
(1)
V
V
CC
R
R
R
CC
DECODER
V
CC
MBA349
V
V
CC
CC
OUT
MR
S1 S2
Internal capacitors typical 7 pF each. Including
stray capacitors on pin X1 and X2, total capacitance
will be typical 12 pF per pin.
Fig.4 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: non-standard; bus driver (except for X2)
ICC category: MSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
Tamb(°C)
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 85
−40 to 125 UNIT
VCC
(V)
VI
OTHER
MIN TYP MAX MIN MAX MIN MAX
VIH
VIL
HIGH level
input voltage
MR, X1 input
1.5
3.15 2.4
4.2
1.2
−
−
−
1.5
3.15
4.2
−
−
−
1.50
3.15
4.20
−
−
−
V
V
V
2.0
4.5
6.0
3.2
LOW level
input voltage
MR, X1 input
−
−
−
0.8 0.5
2.1 1.35
2.8 1.80
−
−
−
0.5
1.35
1.8
−
−
−
0.5
1.35
1.8
V
V
V
2.0
4.5
6.0
VOH
HIGH level
output voltage
X2 output
3.98
5.48
−
−
−
−
3.84
5.34
−
−
3.7
5.2
−
−
V
V
4.5 X1 = GND IO = −2.6 mA
6.0 and
MR = VCC
IO = −3.3 mA
3.98
5.48
−
−
−
−
3.84
5.34
−
−
3.7
5.2
−
−
V
V
4.5 X1 = VCC
6.0 and
IO = −2.6 mA
IO = −3.3 mA
MR = GND
1.9
4.4
5.9
2.0
4.5
6.0
−
−
−
1.9
4.4
5.9
−
−
−
1.9
4.4
5.9
−
−
−
V
V
V
2.0 X1 = GND −IO = 20 µA
4.5 and IO = −20 µA
6.0 MR = VCC IO = −20 µA
1.9
4.4
5.9
2.0
4.5
6.0
−
−
−
1.9
4.4
5.9
−
−
−
1.9
4.4
5.9
−
−
−
V
V
V
2.0 X1 = VCC
4.5 and
6.0 MR = GND IO = −20 µA
IO = −20 µA
IO = −20 µA
VOH
VOH
VOL
HIGH level
output voltage
OUT
1.9
4.4
5.9
2.0
4.5
6.0
−
−
−
1.9
4.4
5.9
−
−
−
1.9
4.4
5.9
−
−
−
V
V
V
2.0 VIH or VIL
4.5
6.0
IO = −20 µA
IO = −20 µA
IO = −20 µA
HIGH level
output voltage
OUT
3.98
5.48
−
−
−
−
3.84
5.34
−
−
3.7
5.2
−
−
V
V
4.5 VIH or VIL
6.0
IO = −6 mA
IO = −7.8 mA
LOW level
output voltage
X2 output
−
−
−
−
0.26
0.26
−
−
0.33
0.33
−
−
0.4
0.4
V
V
4.5 X1 = VCC
6.0 and
IO = 2.6 mA
IO = 3.3 mA
MR = VCC
−
−
−
0
0
0
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
V
V
V
2.0 X1 = VCC
4.5 and
6.0 MR = VCC IO = 20 µA
IO = 20 µA
IO = 20 µA
VOL
LOW level
output voltage
OUT
−
−
−
0
0
0
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
V
V
V
2.0 VIH or VIL
4.5
6.0
IO = 20 µA
IO = 20 µA
IO = 20 µA
September 1993
5
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
Tamb(°C)
−40 to 85
MIN TYP MAX MIN MAX MIN MAX
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 125 UNIT
VCC
(V)
VI
OTHER
VOL
±ILI
−II
LOW level
output voltage
OUT
−
−
−
−
0.26
0.26
−
−
0.33
0.33
−
−
0.4
0.4
V
V
4.5 VIH or VIL
6.0
IO = 6 mA
IO = 7.8 mA
input leakage
current X1
−
5
−
−
0.1
100
8
−
−
−
1
−
−
−
1
µA
µA
6.0 MR = VCC
S1 = VCC
S2 = VCC
input pull-up
current S1, S2
and MR
30
−
−
−
6.0 GND
see Fig.11
and Fig.12
ICC
quiescent
supply current
80
160 µA
6.0 VCC or
GND
IO = 0
September 1993
6
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
−40 to 85
MIN TYP MAX MIN MAX MIN MAX
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 125 UNIT
VCC
(V)
VI
OTHER
t
PHL/tPLH propagation
delay X1 to
−
−
61
22
19
185
37
31
−
−
−
230
46
39
−
−
−
275 ns
2.0
4.5
6.0
Fig.7 S1 = GND
S2 = GND
55
47
ns
ns
OUT divide by 1 −
tPHL/tPLH propagation
delay X1 to
−
−
74
27
23
235
47
40
−
−
−
290
58
49
−
−
−
350 ns
2.0
4.5
6.0
Fig.7 S1 = GND
S2 = VCC
70
60
ns
ns
OUT divide by 2 −
tPHL/tPLH propagation
delay X1 to
−
−
91
33
28
285
57
48
−
−
−
355
71
60
−
−
−
425 ns
2.0
4.5
6.0
Fig.7 S1 = VCC
S2 = GND
85
72
ns
ns
OUT divide by 4 −
t
PHL/tPLH propagation
delay X1 to
−
−
105 335
−
−
−
415
83
71
−
−
−
500 ns
100 ns
2.0
4.5
6.0
Fig.7 S1 = VCC
S2 = VCC
38
32
67
57
OUT divide by 8 −
85
ns
tPLZ/tPHZ
tPZL
tPZH
tTHL/tTLH
tW
3-state output
disable time
MR to OUT
−
−
−
75
15
13
150
30
26
−
−
−
185
37
31
−
−
−
225 ns
2.0
4.5
6.0
Fig.8
45
38
ns
ns
3-state output
enable time
MR to OUT
−
−
−
36
13
11
150
30
26
−
−
−
185
37
31
−
−
−
225 ns
2.0
4.5
6.0
Fig.8
45
38
ns
ns
3-state output
enable time
MR to OUT
−
−
−
61
22
19
200
40
34
−
−
−
250
50
43
−
−
−
300 ns
2.0
4.5
6.0
Fig.8 note 1
Fig.7
60
51
ns
ns
output
transition time
−
−
−
14
5
4
60
12
10
−
−
−
75
15
13
−
−
−
90
19
15
ns
ns
ns
2.0
4.5
6.0
clock pulse
width X1,
HIGH or LOW
50
10
9
17
6.0
5
−
−
−
60
12
10
−
−
−
75
15
13
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.7
tW
master reset
pulse width
MR; LOW
80
16
14
22
8
7
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.9
trem
removal time
MR to X1
100 19
−
−
−
125
25
21
−
−
−
150
30
26
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.9
20
17
7
6.0
fmax
maximum clock 10
pulse frequency 50
59
17
85
100
−
−
−
8
40
47
−
−
−
6.6
33
39
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Fig.7
Note to the 74HC AC Characteristics
1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
September 1993
7
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver (except for X2).
ICC category: MSI.
Voltages are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 85
−40 to 125 UNIT
VCC
(V)
VI
OTHER
MIN TYP MAX MIN MAX MIN MAX
VIH
HIGH level
input voltage
MR, S1 and
S2 inputs
2.0
−
−
−
2.0
−
2.0
−
V
V
4.5
to
5.5
VIL
LOW level
input voltage
MR, S1 and
S2 inputs
−
0.8
−
0.8
−
0.8
4.5
to
5.5
VIH
VIL
HIGH level
input voltage
X1 input
3.15
3.85
−
−
−
−
3.15
3.85
−
−
3.15
3.85
−
−
V
V
4.5
5.5
LOW level
input voltage
X1 input
−
−
−
−
1.35
1.65
−
−
1.35
1.65
−
−
1.35
1.65
V
V
4.5
5.5
VOH
HIGH level
output voltage
X2 output
3.98
3.98
4.4
−
−
−
−
−
−
−
3.84
3.84
4.4
−
−
−
−
−
−
3.7
3.7
4.4
4.4
4.4
3.7
−
−
−
−
−
−
V
V
V
V
V
V
4.5 X1 = GND IO = −2.6 mA
and
MR = VCC
−
4.5 X1 = VCC
and
IO = −2.6 mA
MR = GND
4.5
4.5
4.5
−
4.5 X1 = GND IO = −20 µA
and
MR = VCC
4.4
4.4
4.5 X1 = VCC
and
IO = −20 mA
IO = −20 µA
IO = −6 mA
MR = GND
VOH
HIGH level
output voltage
OUT
4.4
4.4
4.5 VIH or VIL
VOH
HIGH level
output voltage
OUT
3.98
3.84
4.5 VIH or VIL
September 1993
8
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
Tamb (°C)
−40 to 85
MIN TYP MAX MIN MAX MIN MAX
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 125 UNIT
VCC
(V)
VI
OTHER
VOL
LOW level
output
voltage X2
output
−
−
−
−
−
5
−
0.26
0.1
0.1
0.26
0.1
100
8
−
−
−
−
−
−
0.33
0.1
0.1
0.33
1.0
−
−
−
−
−
−
−
0.4
0.1
0.1
0.4
1.0
−
V
4.5 X1 = VCC
and
IO = 2.6 mA
MR = VCC
0
V
4.5 X1 = VCC
and
IO = 20 µA
IO = 20 µA
IO = 6 mA
MR = VCC
VOL
VOL
±ILI
−II
LOW level
output voltage
OUT
0
V
4.5 VIH or VIL
LOW level
output voltage
OUT
−
V
4.5 VIH or VIL
input leakage
current
−
µA
µA
5.5 MR = VCC;
S1 = VCC;
S2 = VCC
input pull-up
current S1, S2
and MR
25
−
5.5 GND
see Fig.11
and Fig.12
ICC
quiescent
supply current
−
−
−
−
80
−
−
160 µA
490 µA
5.5 VCC or
GND
Io = 0
∆ICC
additional
quiescent
100 360
450
5.5
VCC or
other inputs
at VCC or
GND
supply current
per input pin
for unit load
coefficient is 1
GND; Io = 0;
(note 1)
Note to the HCT DC Characteristics
1. The value of additional quiescent supply current (∆ICC) for unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
INPUT
UNIT LOAD COEFFICIENT
MR, S1, S2
0.40
September 1993
9
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
−40 to 85
MIN TYP MAX MIN MAX MIN MAX
TEST CONDITION
SYMBOL PARAMETER
25
−40 to 125 UNIT
VCC
(V)
VI
OTHER
t
PHL/tPLH propagation
delay X1 to
−
−
−
−
24
29
35
40
40
50
60
70
−
−
−
−
50
62
75
87
−
−
−
−
60
75
90
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.7 S1 = GND
S2 = GND
OUT
divide-by-1
t
PHL/tPLH propagation
Fig.7 S1 = GND
S2 = VCC
delay X1 to
OUT
divide-by-2
tPHL/tPLH propagation
delay X1 to
Fig.7 S1 = VCC
S2 = GND
OUT
divide-by-4
t
PHL/tPLH propagation
delay X1 to
105 ns
Fig.7 S1 = VCC
S2 = VCC
OUT
divide-by-8
tPLZ/tPHZ
3-state output
disable time
MR to OUT
−
−
−
21
16
22
35
30
38
−
−
−
43
37
47
−
−
−
52
45
57
ns
ns
ns
4.5
4.5
4.5
Fig.8
tPZ
3-state output
enable time
MR to OUT
Fig.8
tPZH
3-state output
enable time
MR to OUT
Fig.8 see note 1
tTHL/tTLH
tW
output
transition time
−
5
6
12
−
15
−
19
ns
ns
4.5
4.5
Fig.7
Fig.7
clock pulse
width X1,
10
−
12
−
15
−
HIGH or LOW
tW
master reset
pulse width
MR; LOW
16
24
8
−
20
−
24
−
ns
ns
4.5
4.5
Fig.9
trem
fmax
removal time
MR to X1
12
85
−
−
30
40
−
−
36
33
−
−
Fig.9
Fig.7
maximum clock 50
pulse frequency
MHz 4.5
Note to the 74HCT AC Characteristics
1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
September 1993
10
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
MBA331
24
handbook, halfpage
g
fs
(mA/V)
20
16
12
8
R
= 560 kΩ
bias
handbook, halfpage
V
CC
0.47 µF
100 F
µ
output
input
v
i
i
A
o
(f = 1 kHz)
4
GND
MGA645
0
0
1
2
3
4
5
6
V
(V)
CC
Fig.6 Typical forward transconductance gfs as a
function of the supply voltage Vcc at
Tamb = 25 °C.
Fig.5 Test set-up for measuring forward
transconductance gfs = dio/dvi at
vo is constant (see also Fig.6); MR = HIGH.
1/f max
(1)
V
t
X1 INPUT
M
t
W
PHL
t
PLH
(1)
OUT OUTPUT
V
M
t
t
THL
TLH
MBA318
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (X1) to output (OUT) propagation delays, the clock pulse width,
the output transition times and the maximum clock frequency.
September 1993
11
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
t
t
r
f
90 %
(1)
MR INPUT
V
M
10 %
t
t
PZL
PLZ
OUTPUT
LOW - to - OFF
OFF - to - LOW
(1)
V
M
t
t
PZH
PHZ
90 %
OUTPUT
(1)
HIGH - to - OFF
OFF - to - HIGH
V
M
outputs
enabled
outputs
disabled
outputs
enabled
MBA319
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input MR to output OUT, 3-state enable and disable times.
t
W
handbook, halfpage
(1)
V
MR INPUT
M
t
rem
(1)
V
X1 INPUT
M
MBA323
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the MR minimum pulse width and MR to X1 removal time.
September 1993
12
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
APPLICATION INFORMATION
MBA347
40
handbook, halfpage
−I
I
(µA)
V
= 6 V
4.3 V
2 V
CC
30
handbook, halfpage
6323A
20
10
0
5
MR
MBA348
0
1
2
3
4
5
6
V (V)
I
The input pull-up current is used to create a
power-on delay time at MR.
Fig.11 Typical input pull-up current as a function
of the input voltage (VI).
Fig.10 Power-on reset.
Table 1 Typical application values
f (MHz)
R2 (kΩ)
C1 (pF)
47 to 68
47 to 68
33
C2 (pF)
1
4.7
2.2
1
MBA346
50
10
25
handbook, halfpage
−I
I
33
(µA)
40
Table 2 Typical Application Values
30
20
f (MHz)
R
bias (kΩ)
C1 (pF)
50
3.0
4.7
V = 0 V
I
10
0
1
2
3
4
5
6
V
(V)
CC
Fig.12 Typical input pull-up current as a function of
the supply voltage (VCC).
September 1993
13
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
handbook, halfpage
MR (from logic)
handbook, halfpage
MR (from logic)
X1
7
X1
7
X2
6
X2
6
R
R
bias
bias
100 kΩ to 1
3 kΩ
R2
2.2
MΩ
kΩ
22 to
37 pF
1 to 10 pF
(optional)
C1
C2
100 pF
C1
MBA329 - 1
MBA328 - 1
Applicable for third overtone crystals (lower
damping resistance at the third harmonic
frequency) at typical 50 MHz. For lower
frequencies extra load capacitors must be
supplied, or increase bias resistor.
Above 5 MHz replace R2 by a capacitor of
half the value of C2.
CL at which a crystal is specified (or adjusted)
equals for this application C1 . C2/C1 + C2.
Fig.14 Typical set-up for a crystal oscillator
operating in the third overtone mode without
the use of an inductor.
Fig.13 Typical setup for a crystal oscillator
operating in the fundamental mode
(1 MHz to 25 MHz).
September 1993
14
Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
Typical Crystal Oscillator
Considerations for Fundamental
Oscillator:
Considerations for Third-overtone
Oscillator:
In Fig.13, R2 is the power limiting
resistor. For starting and maintaining
oscillation a minimum
transconductance is necessary, so
R2 should not be too large. A practical
value for R2 is 2.2 kΩ.
In the fundamental oscillator mode,
the Rb has only the function of biasing
the inverter stage, so that it operates
as an amplifier with a phase shift of
approximately 180°. The value must
be high, i.e. 100 kΩ up to 10 MΩ. The
load capacitors C1 and C2, must
have a value that is suitable for the
crystal being used. The crystal is
designed for a certain frequency
having a specific load capacitance.
C1 can be used to trim the oscillation
frequency. The series resistance
reduces the total loop gain. One
function of it is therefore to reduce the
power dissipation in the crystal. Rs
also suppresses overtone oscillations
and introduces a phase shift over a
broad frequency range. This is of less
concern provided Rs is not too high a
value.
In the overtone configuration, series
resistance is no longer applied. This
is essential otherwise the gain for
third overtone can be too small for
oscillation. A simple solution to
suppress the fundamental oscillation,
is to spoil the crystal fundamental
activity. By dramatically reducing the
value of the bias resistor of the
inverting stage, and applying small
load capacitors, it is possible to have
an insufficient phase in the total loop
for fundamental oscillation. However
the phase for third overtone is good. It
can be explained by the Rb × Cl time
constant. During oscillation the
crystal with the load capacitors cause
a phase shift of 180°. Because Rb is
parallel with the crystal (no Rs), Rb
spoils the phase for fundamental.
Rb × Cl must be of a value, that it is
not spoiling the phase for third
The oscillator has been designed to
operate over a wide frequency
spectrum, for quartz crystals
operating in the fundamental mode
and in the overtone mode. The circuit
is a Pierce type oscillator and requires
a minimum of external components.
There are two on-chip capacitors, X1
and X2, of approximately 7 pF.
Together with the stray and input
capacitance the value becomes 12 pF
for 8-pin SO packages. These values
are convenient and make it possible
to run the oscillator in the third
overtone without external capacitors
applied. If a certain frequency is
chosen, the IC parameters, as
forward transconductance, and the
crystal parameters such as the
motional resistances R1
overtone too much. Because third
overtone is a 3 times higher
Note
A combination of a small load
capacitor value and a small series
resistance, may cause a third
overtone oscillation.
frequency than the fundamental, the
Rb × Cl cannot 'maintain' the higher
third overtone frequency, which
results in a less spoiled overtone
phase.
(fundamental), R3 (third overtone)
and R5 (fifth overtone), are of
paramount importance. Also the
values of the external components as
Rs (series resistance) and the crystal
load capacitances play an important
role. Especially in overtone mode
oscillations, Rb (bias resistance) and
the load capacitance values are very
important.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic
Package Outlines”.
September 1993
15
相关型号：
©2020 ICPDF网 联系我们和版权申明