74HCT643D-T [NXP]
IC HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver;
| 型号： | 74HCT643D-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver 总线收发器 |
| 文件： | 总6页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT643
Octal bus transceiver; 3-state;
true/inverting
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
FEATURES
GENERAL DESCRIPTION
• Octal bidirectional bus interface
• True and inverting 3-state outputs
• Output capability: bus driver
• ICC category: MSI
The 74HC/HCT643 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT643 are octal transceivers featuring true
and inverting 3-state bus compatible outputs in both send
and receive directions.
The “643” features an output enable (OE) input for easy
cascading and a send/receive (DIR) for direction control.
OE controls the outputs so that the buses are effectively
isolated.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
t
tPHL
/
CL = 15 pF; VCC = 5 V
PLH
An to Bn; inverting
Bn to An; true
7
8
8
11
ns
ns
pF
pF
pF
CI
input capacitance
3.5
10
42
3.5
10
44
CI/O
input/output capacitance
CPD
power dissipation capacitance per transceiver notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
PIN DESCRIPTION
PIN NO.
SYMBOL NAME AND FUNCTION
1
DIR
direction control
2, 3, 4, 5, 6, 7, 8, 9
10
A0 to A7
GND
data inputs/outputs
ground (0 V)
18, 17, 16, 15, 14, 13, 12, 11 B0 to B7
data inputs/outputs
output enable input (active LOW)
positive supply voltage
19
20
OE
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
FUNCTION TABLE
INPUTS
OE DIR
INPUTS/OUTPUTS
An
Bn
L
L
H
L
H
X
A = B
inputs
Z
inputs
B = A
Z
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
December 1990
3
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Bn;
25
9
7
90
18
15
115
23
20
135
27
23
ns
ns
ns
ns
ns
2.0 Fig.5
4.5
6.0
inverting
t
t
t
t
PHL/ tPLH propagation delay
Bn to An;
28
10
8
90
18
15
115
23
20
135
27
23
2.0 Fig.6
4.5
6.0
non-inverting (true)
PZH/ tPZL 3-state output enable time
OE, DIR to An;
39
14
11
150
30
26
190
38
33
225
45
38
2.0 Fig.7
4.5
6.0
OE, DIR to Bn
PHZ/ tPLZ 3-state output disable time
OE, DIR to An;
44
16
13
150
30
26
190
38
33
225
45
38
2.0 Fig.7
4.5
6.0
OE, DIR to Bn
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.5 and Fig.6
4.5
6.0
December 1990
4
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1.50
An
Bn
OE
DIR
0.40
1.50
0.90
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Bn;
10
13
16
17
5
20
23
30
30
12
25
29
38
38
15
30
35
45
45
18
ns
ns
ns
ns
ns
4.5 Fig.5
inverting
t
t
t
t
PHL/ tPLH propagation delay
Bn to An;
4.5 Fig.6
non-inverting (true)
PZH/ tPZL 3-state output enable time
OE, DIR to An;
4.5 Fig.7
OE, DIR to Bn
PHZ/ tPLZ 3-state output disable time
OE, DIR to An;
4.5 Fig.7
OE, DIR to Bn
THL/ tTLH output transition time
4.5 Fig.5 and Fig.6
December 1990
5
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (Bn) to
output (An) propagation delays and the
output transition times.
Fig.5 Waveforms showing the input (An) to output
(Bn) propagation delays and the output
transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and
disable times for OE and DIR inputs.
December 1990
6
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