74HCT670D,653 [NXP]
4X4 STANDARD SRAM, 60ns, PDSO16;
| 型号： | 74HCT670D,653 |
| 厂家： | 
NXP |
| 描述： | 4X4 STANDARD SRAM, 60ns, PDSO16 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT670
4 x 4 register file; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q0 to Q3). Dn and Wn inputs are inhibited when
WE is HIGH.
FEATURES
• Simultaneous and independent read and write
operations
• Expandable to almost any word size and bit length
• Output capability: bus driver
• ICC category: MSI
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(RA and RB). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
organized as 4 words of 4 bits each. Separated read and
write address inputs (RA, RB and WA, WB) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D0 to D3). The WA and WB inputs determine
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
23
tPHL/ tPLH propagation delay Dn to Qn
CL = 15 pF; VCC = 5 V
23
CI
input capacitance
3.5
3.5
pF
pF
CPD
power dissipation capacitance per package
notes 1 and 2
122
124
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
;
for HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
5, 4
RA, RB
GND
read address inputs
8
ground (0 V)
10, 9, 7, 6
11
Q0 to Q3
RE
data outputs
3-state output read enable input (active LOW)
write enable input (active LOW)
write address inputs
data inputs
12
WE
14, 13
15, 1, 2, 3
16
WA, WB
D0 to D3
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
WRITE MODE SELECT TABLE
INPUTS
READ MODE SELECT TABLE
OPERATING
INPUTS
OUTPUT
Qn
OPERATING
MODE
INTERNAL
LATCHES(1)
MODE
WE Dn
RE
INTERNAL LATCHES(1)
L
L
L
H
L
H
L
L
L
H
L
H
write data
read
data latched
H
X
no change
disabled
H
X
Z
Note
Notes
1. The write address (WA and WB) to the
“internal latches” must be stable while WE is
LOW for conventional operation.
1. The selection of the “internal latches” by read address
(RA and RB) are not constrained by WE or RE operation.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
December 1990
3
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
DC CHARACTERISTICS FOR 74HC
74HC/HCT670
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to+125
WAVEFORMS
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
58
21
17
195
39
33
245
49
42
295
59
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
RA, RB to Qn
tPHL/ tPLH propagation delay
WE to Qn
77
28
22
250
50
43
315
63
54
375
75
64
2.0 Fig.7
4.5
6.0
t
PHL/ tPLH propagation delay
Dn to Qn
74
27
22
250
50
43
315
63
54
375
75
64
2.0 Fig.7
4.5
6.0
tPZH/ tPZL 3-state output enable time
RE to Qn
39
14
11
150
30
26
190
38
33
225
45
38
2.0 Fig.9
4.5
6.0
t
t
PHZ/ tPLZ 3-state output disable time
RE to Qn
47
17
14
150
30
26
190
38
33
225
45
38
2.0 Fig.9
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.6
4.5
6.0
tW
tsu
tsu
th
write enable pulse width
LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
Dn to WE
60
12
10
3
1
1
75
15
13
90
18
15
2.0 Fig.8
4.5
6.0
set-up time
WA, WB to WE
60
12
10
6
2
2
75
15
13
90
18
15
2.0 Fig.8
4.5
6.0
hold time
Dn to WE
5
5
5
0
0
0
5
5
5
5
5
5
2.0 Fig.8
4.5
6.0
th
hold time
WA, WB to WE
5
5
5
0
0
0
5
5
5
5
5
5
2.0 Fig.8
4.5
6.0
tlatch
latch time
WE to RA, RB
100 28
125
25
21
150
30
26
2.0 Fig.8
4.5
6.0
20
17
10
8
December 1990
5
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
WE, WA
WB
0.25
0.40
0.60
RA
RB
RE
0.70
1.10
1.35
December 1990
6
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
RA, RB to Qn
21
28
27
18
19
5
40
50
50
35
35
12
50
63
63
44
44
15
60
75
75
53
53
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.9
4.5 Fig.9
4.5 Fig.6
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
t
PHL/ tPLH propagation delay
WE to Qn
t
PHL/ tPLH propagation delay
Dn to Qn
tPZH/ tPZL 3-state output enable time
RE to Qn
t
PHZ/ tPLZ 3-state output disable time
RE to Qn
t
THL/ tTLH output transition time
tW
tsu
tsu
th
write enable pulse width
LOW
18
12
12
5
9
23
15
15
5
27
18
18
5
set-up time
Dn to WE
4
set-up time
WA, WB to WE
−2
−1
0
hold time
Dn to WE
th
hold time
5
5
5
WA, WB to WE
tlatch
latch time
25
11
31
38
WE to RA, RB
December 1990
7
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the write enable input
(WE) and data input (Dn) to output (Qn)
propagation delays, and the write enable
pulse width.
Fig.6 Waveforms showing the read address input
(RA, RB) to output (Qn) propagation delays
and output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
The time allowed for the internal output of the latch to
assume the state of the new data (tlatch) is important
only when attempting to read from a location
immediately after that location has received new data.
This parameter is measured from the falling edge of
WE to the rising edge of RA or RB, RE must be LOW.
Fig.8 Waveforms showing the write address input (WA, WB) and data input (Dn) to write enable (WE) set-up,
hold and latch times.
December 1990
8
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the read enable (RE) to output (Qn) enable and disable times, and the read enable
pulse width.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
9
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