74HCT7046AP [NXP]
IC PHASE LOCKED LOOP, PDIP16, PLASTIC, SOT-38CP, DIP-16, PLL or Frequency Synthesis Circuit;型号: | 74HCT7046AP |
厂家: | NXP |
描述: | IC PHASE LOCKED LOOP, PDIP16, PLASTIC, SOT-38CP, DIP-16, PLL or Frequency Synthesis Circuit |
文件: | 总38页 (文件大小:492K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7046A
Phase-locked-loop with lock
detector
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
amplifiers. With a passive low-pass
SIGIN (pin 14) or COMPIN (pin 3)
inputs between the HC and HCT
versions.
FEATURES
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
• Low power consumption
• Centre frequency up to 17 MHz
(typ.) at VCC = 4.5 V
Phase comparators
• Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
The signal input (SIGIN) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
VCO
The VCO requires one external
capacitor C1 (between C1A and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
• Excellent VCO frequency linearity
• VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
Capacitive coupling is required for
signals with smaller swings.
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
• Minimal frequency drift
Phase comparator 1 (PC1)
• Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (fi) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is
suppressed,
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
• Zero voltage offset due to op-amp
buffering
• Output capability: standard
• ICC category: MSI
is:
V
VDEMOUT
=
CC (φ SIGIN – φCOMPIN
)
----------
π
GENERAL DESCRIPTION
(DEMOUT). In contrast to conventional
techniques where the DEMOUT
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEMOUT voltage equals that of the
VCO input. If DEMOUT is used, a load
resistor (RS) should be connected
from DEMOUT to GND; if unused,
DEMOUT should be left open. The
VCO output (VCOOUT) can be
connected directly to the comparator
input (COMPIN), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
where VDEMOUT is the demodulator
output at pin 10;
The 74HC/HCT7046 are
VDEMOUT = VPC1OUT (via low-pass
filter).
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
The phase comparator gain
is:
VCC
Kp
=
(V ⁄ r) .
----------
π
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
between pin 15 (CLD) and pin 8
(GND). The value of the CLD capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
demodulator output at pin 10
(VDEMOUT), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
VDEMOUT is equal to 1/2 VCC when
there is no signal or noise at SIGIN
and with this input the VCO oscillates
at the centre frequency (fo). Typical
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the
December 1990
2
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
waveforms for the PC1 loop locked at
fo are shown in Fig.7.
the low-pass filter. With no signal
present at SIGIN the VCO adjusts, via
PC2, to its lowest frequency.
The phase comparator gain is:
V
Kp
=
CC (V ⁄ r) .
----------
The frequency capture range (2fc) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2fL) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
4π
APPLICATIONS
V
DEMOUT is the resultant of the initial
• FM modulation and demodulation
phase differences of SIGIN and
COMPIN as shown in Fig.8. Typical
waveforms for the PC2 loop locked at
fo are shown in Fig.9.
• Frequency synthesis and
multiplication
• Frequency discrimination
• Tone decoding
When the frequencies of SIGIN and
COMPIN are equal but the phase of
SIGIN leads that of COMPIN, the
p-type output driver at PC2OUT is held
“ON” for a time corresponding to the
phase difference (φDEMOUT). When
the phase of SIGIN lags that of
• Data synchronization and
conditioning
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.
• Voltage-to-frequency conversion
• Motor-speed control
COMPIN, the n-type driver is held
“ON”.
When the frequency of SIGIN is higher
than that of COMPIN, the p-type
output driver is held “ON” for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are “OFF” (3-state). If
the SIGIN frequency is lower than the
COMPIN frequency, then it is the
n-type driver that is held “ON” for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2OUT
varies until the signal and comparator
inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
Phase comparator 2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIGIN and COMPIN are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIGIN
causes an up-count and COMPIN
a
down-count. The transfer function of
PC2, assuming ripple (fr = fi) is
suppressed,
is:
impedance.
V
Thus, for PC2, no phase difference
exists between SIGIN and COMPIN
over the full frequency range of the
VCO. Moreover, the power
VDEMOUT
=
CC (φ SIGIN – φCOMPIN
)
----------
4π
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are “OFF” for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of
where VDEMOUT is the demodulator
output at pin 10;
VDEMOUT = VPC2OUT (via low-pass
filter).
December 1990
3
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C;
TYPICAL
UNIT
SYMBOL PARAMETER
CONDITIONS
HC
HCT
fo
VCO centre frequency
C1 = 40 pF; R1 = 3 kΩ; VCC = 5 V
19
19
MHz
pF
CI
input capacitance (pin 5)
3.5
24
3.5
24
CPD
power dissipation capacitance per package notes 1 and 2
pF
Notes
1. Applies to the phase comparator section only (VCO disabled).
For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.
2. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
4
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
lock detector output (active HIGH)
phase comparator 1 output
comparator input
1
LD
2
PC1OUT
COMPIN
VCOOUT
INH
3
4
VCO output
5
inhibit input
6
C1A
capacitor C1 connection A
capacitor C1 connection B
ground (0 V)
7
C1B
8
GND
VCOIN
DEMOUT
R1
9
VCO input
10
11
12
13
14
15
16
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
R2
PC2OUT
SIGIN
CLD
lock detector capacitor input
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
5
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
GM8A47
December 1990
6
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.5 Logic diagram.
Fig.6 Phase comparator 1: average output
voltage versus input phase difference:
V
VDEMOUT = VPC1OUT
=
CC (φ SIGIN – φCOMPIN
)
----------
π
Fig.7 Typical waveforms for PLL using phase
comparator 1, loop locked at fo.
φDEMOUT = φSIGIN – φCOMPIN
December 1990
7
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.8 Phase comparator 2: average output
voltage versus input phase difference:
V
VDEMOUT = VPC2OUT
=
CC (φ SIGIN – φCOMPIN
)
----------
4π
Fig.9 Typical waveforms for PLL using phase
comparator 2, loop locked at fo.
˙
φDEMOUT = (φSIGIN – φCOMPIN) .
December 1990
8
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
74HC
74HCT
SYMBOL PARAMETER
UNIT CONDITIONS
min. typ. max. min. typ. max.
VCC
VCC
DC supply voltage
3.0
2.0
5.0
5.0
6.0
6.0
4.5
4.5
5.0
5.0
5.5
5.5
V
V
DC supply voltage if VCO section is
not used
VI
DC input voltage range
DC output voltage range
0
0
VCC
VCC
+85
0
VCC
VCC
+85
V
VO
0
V
Tamb
Tamb
operating ambient temperature range −40
operating ambient temperature range −40
−40
°C
see DC and AC
CHARACTER-
ISTICS
+125 −40
+125 °C
tr, tf
input rise and fall times (pin 5)
1000
500
VCC = 2.0 V
6.0
6.0
500
ns
VCC = 4.5 V
400
VCC = 6.0 V
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
VCC
PARAMETER
MIN. MAX. UNIT CONDITIONS
DC supply voltage
−0.5 +7
V
±IIK
DC input diode current
DC output diode current
DC output source or sink current
DC VCC or GND current
20
20
25
mA
mA
mA
for VI < −0.5 V or VI > VCC + 0.5 V
for VO < −0.5 V or VO > VCC + 0.5 V
for − 0.5 V < VO < VCC + 0.5 V
±IOK
±IO
±ICC
±IGND
;
50
mA
Tstg
storage temperature range
−65
+150 °C
Ptot
power dissipation per package
for temperature range: −40 to +125 °C
74HC/HCT
plastic DIL
750
500
mW
mW
above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
above +70 °C: derate linearly with 8 mW/K
December 1990
9
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HC
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
OTHER
min. typ. max. min. max. min. max.
8.0 80.0 160.0 µA
ICC
quiescent supply
current
(VCO disabled)
6.0 pins 3, 5, and 14 at
VCC; pin 9 at GND;
II at pins 3 and 14
to be excluded
December 1990
10
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC VI
(V)
+25
−40 to +85 −40 to +125
OTHER
min. typ. max. min. max. min. max.
DC coupled HIGH
level input voltage
SIGIN, COMPIN
1.5
3.15 2.4
4.2
1.2
1.5
3.15
4.2
1.5
3.15
4.2
2.0
4.5
6.0
VIH
V
V
V
V
V
3.2
DC coupled LOW level
input voltage
SIGIN, COMPIN
0.8
2.1
2.8
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
2.0
4.5
6.0
VIL
HIGH level output
voltage
LD, PCnOUT
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
2.0 VIH −IO = 20 µA
4.5 or −IO = 20 µA
6.0 VIL −IO = 20 µA
VOH
VOH
VOL
HIGH level output
voltage
LD, PCnOUT
VIH
or
VIL
3.98 4.32
5.48 5.81
3.84
5.34
3.7
5.2
4.5
6.0
−IO = 4.0 mA
−IO = 5.2 mA
LOW level output
voltage
LD, PCnOUT
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
2.0 VIH IO = 20 µA
4.5 or IO = 20 µA
6.0 VIL IO = 20 µA
LOW level output
voltage
LD, PCnOUT
VIH
or
VIL
0.15 0.26
0.16 0.26
0.33
0.33
0.4
0.4
4.5
6.0
IO = 4.0 mA
IO = 5.2 mA
VOL
V
±II
input leakage current
SIGIN, COMPIN
3.0
7.0
18.0
30.0
4.0
9.0
23.0
38.0
5.0
µA
2.0 VCC
3.0 or
4.5 GND
6.0
11.0
27.0
45.0
±IOZ
3-state
0.5
5.0
10.0 µA
6.0 VIH VO = VCC
OFF-state current
PC2OUT
or
VIL
or GND
RI
input resistance
SIGIN, COMPIN
800
250
150
kΩ
3.0 VI at self-bias
4.5 operating point;
6.0 ∆VI = 0.5 V; see
Figs 10, 11 and 12
December 1990
11
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
VCO section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYM-
BOL
PARAMETER
UNIT
VCC VI
OTHER
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
HIGH level
input voltage
INH
2.1
3.15 2.4
4.2
1.7
2.1
3.15
4.2
2.1
3.15
4.2
3.0
4.5
6.0
VIH
VIL
V
3.2
LOW level
input voltage
INH
1.3
2.1
2.8
0.9
1.35
1.8
0.9
1.35
1.8
0.9
1.35
1.8
3.0
4.5
6.0
V
HIGH level
output voltage
VCOOUT
2.9
4.4
5.9
3.0
4.5
6.0
2.9
4.4
5.9
2.9
4.4
5.9
3.0 VIH −IO = 20 µA
VOH
VOH
VOL
VOL
VOL
±II
V
4.5 or
−IO = 20 µA
6.0 VIL −IO = 20 µA
HIGH level
output voltage
VCOOUT
VIH
or
VIL
3.98 4.32
5.48 5.81
3.84
5.34
3.7
5.2
4.5
6.0
−IO = 4.0 mA
−IO = 5.2 mA
V
LOW level
output voltage
VCOOUT
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0 VIH IO = 20 µA
4.5 or IO = 20 µA
6.0 VIL IO = 20 µA
V
LOW level
output voltage
VCOOUT
VIH
or
VIL
0.15 0.26
0.16 0.26
0.33
0.33
0.4
0.4
4.5
6.0
IO = 4.0 mA
IO = 5.2 mA
V
LOW level output
voltage C1A, C1B
(test purposes only)
VIH
or
VIL
0.40
0.40
0.47
0.47
0.54
0.54
4.5
6.0
IO = 4.0 mA
IO = 5.2 mA
V
VCC
input leakage current
INH, VCOIN
0.1
1.0
1.0
µA
kΩ
kΩ
pF
6.0 or
GND
3.0
3.0
3.0
300
300
300
3.0
4.5
6.0
R1
resistor range
resistor range
capacitor range
note 1
note 1
3.0
3.0
3.0
300
300
300
3.0
4.5
6.0
R2
40
40
40
3.0
4.5
6.0
no
limit
C1
over the range
specified for R1;
for linearity see
Figs 18 and 19.
1.1
1.1
1.1
1.9
3.4
4.9
3.0
4.5
6.0
operating voltage
range at VCOIN
VVCOIN
V
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
December 1990
12
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
OTHER
min. typ. max. min. max. min. max.
RS
resistor range
50
50
50
300
300
300
kΩ
mV
Ω
3.0 at RS > 300 kΩ
4.5 the leakage
6.0 current can
influence
VDEMOUT
VOFF
offset voltage
VCOIN to VDEMOUT
±30
±20
±10
3.0 VI = VVCOIN
4.5 1/2 VCC
=
;
6.0 values taken
over RS range;
see Fig.13
RD
dynamic output
resistance at DEMOUT
25
25
25
3.0 VDEMOUT =
4.5
6.0
1/2 VCC
December 1990
13
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC CHARACTERISTICS FOR 74HC
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
OTHER
(V)
min. typ. max. min. max. min. max.
t
t
PHL/ tPLH propagation delay
SIGIN, COMPIN
58
21
17
200
40
34
250
50
43
300 ns
60
51
2.0
4.5
6.0
Fig.14
to PC1OUT
PZH/ tPZL 3-state output enable
time SIGIN, COMPIN
to PC2OUT
74
27
22
280
56
48
350
70
60
420 ns
84
71
2.0
4.5
6.0
Fig.15
tPHZ/ tPLZ 3-state output disable
time SIGIN, COMPIN
to PC2OUT
96
35
28
325
65
55
405
81
69
490 ns
98
83
2.0
4.5
6.0
Fig.15
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.14
VI(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIGIN or COMPIN
9
mV
2.0
3.0
4.5
6.0
fi = 1 MHz
11
15
33
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
OTHER
74HC
SYM-
PARAMETER
BOL
UNIT
+25
−40 to +85
−40
to +125
VCC
(V)
min. typ. max. typ. max. min. max.
∆f/T
frequency stability
with temperature
change
0.20
0.15
0.14
%/K 3.0 VI = VVCOIN =1/2 VCC ;
4.5 R1 = 100 kΩ; R2 = ∞;
6.0 C1 = 100 pF; see Fig.16
fo
VCO centre
frequency
7.0
11.0 17.0
10.0
MHz 3.0 VVCOIN = 1/2 VCC
;
4.5 R1 = 3 kΩ; R2 = ∞;
(duty factor = 50%) 13.0 21.0
6.0 C1 = 40 pF; see Fig.17
∆fVCO VCO frequency
1.0
0.4
0.3
%
%
3.0 R1 = 100 kΩ; R2 = ∞;
4.5 C1 = 100 pF; see Figs 18
6.0 and 19
linearity
δVCO
duty factor at
VCOOUT
50
50
50
3.0
4.5
6.0
December 1990
14
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
OTHER
min. typ. max. min. max. min. max.
ICC
quiescent supply current
(VCO disabled)
8.0
80.0
160.0 µA
6.0 pins 3, 5 and 14
at VCC; pin 9 at
GND; II at pins 3
and 14 to be
excluded
∆ICC
additional quiescent
supply current per input
pin for unit load coefficient
is 1 (note 1)
100 360
450
490
µA
4.5 pins 3 and 14 at
to
VCC; pin 9 at
5.5 GND; II at pins 3
and 14 to be
VI = VCC − 2.1 V
excluded
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given above.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
INH
UNIT LOAD COEFFICIENT
1.00
December 1990
15
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
74HCT
−40 to +85 −40 to +125
min. typ. max min. max. min. max.
TEST CONDITIONS
SYM
BOL
PARAMETER
UNIT
VCC VI
(V)
+25
OTHER
DC coupled
VIH
HIGH level input voltage 3.15 2.4
SIGIN, COMPIN
V
4.5
DC coupled
VIL
LOW level input voltage
SIGIN, COMPIN
2.1 1.35
V
4.5
VIH
or
VIL
HIGH level output voltage
LD, PCnOUT
VOH
VOH
VOL
VOL
±II
4.4
4.5
4.4
4.4
3.7
V
4.5
4.5
4.5
4.5
5.5
5.5
−IO = 20 µA
−IO = 4.0 mA
IO = 20 µA
IO = 4.0 mA
VIH
or
VIL
HIGH level output voltage
LD, PCnOUT
3.98 4.32
3.84
V
VIH
or
VIL
LOW level output voltage
LD, PCnOUT
0
0.1
0.1
0.33
38
0.1
0.4
45
V
VIH
or
VIL
LOW level output voltage
LD, PCnOUT
0.15 0.26
V
VCC
or
input leakage current
SIGIN, COMPIN
30
µA
µA
GND
3-state
OFF-state current
PC2OUT
VIH
or
VIL
VO = VCC
or GND
±IOZ
0.5
5.0
10.0
VI at self-bias
input resistance
SIGIN, COMPIN
operating point;
∆VI = 0.5 V; see Figs
10, 11 and 12
RI
250
kΩ
4.5
December 1990
16
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
VCO section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC VI
OTHER
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH
VIL
HIGH level input
voltage
INH
2.0
1.6
2.0
2.0
V
4.5
to
5.5
LOW level input
voltage
INH
1.2 0.8
4.5
0.8
0.8
V
4.5
to
5.5
VOH
VOH
VOL
VOL
VOL
±II
HIGH level output
voltage
VCOOUT
4.4
4.4
4.4
3.7
V
4.5 VIH −IO = 20 µA
or
VIL
HIGH level output
voltage
VCOOUT
3.98 4.32
3.84
V
4.5 VIH −IO = 4.0 mA
or
VIL
LOW level output
voltage
VCOOUT
0
0.1
0.1
0.1
0.4
0.54
1.0
V
4.5 VIH IO = 20 µA
or
VIL
LOW level output
voltage
VCOOUT
0.15 0.26
0.40
0.33
0.47
1.0
V
4.5 VIH IO = 4.0 mA
or
VIL
LOW level output
voltage C1A, C1B
(test purposes only)
V
4.5 VIH IO = 4.0 mA
or
VIL
input leakage
current
0.1
µA
5.5 VCC
or
INH, VCOIN
GND
R1
R2
C1
resistor range
resistor range
capacitor range
3.0
3.0
40
300
300
kΩ
kΩ
pF
4.5
4.5
4.5
note 1
note 1
no
limit
VVCOIN
operating voltage
range at VCOIN
1.1
3.4
V
4.5
over the range
specified for
R1;
for linearity see
Figs 18 and 19.
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
December 1990
17
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
74HCT
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
VCC
+25
OTHER
(V)
RS
resistor range
50
300
kΩ
4.5 at RS > 300 kΩ the
leakage current can
influence VDEMOUT
VOFF
offset voltage
VCOIN to VDEMOUT
±20
mV
4.5 VI = VVCOIN = 1/2
VCC; values taken
over RS range;
see Fig.13
RD
dynamic output
25
Ω
4.5 VDEMOUT = 1/2 VCC
resistance at DEMOUT
AC CHARACTERISTICS FOR 74HCT
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST
CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85
−40 to +125
OTHER
(V)
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
21
27
35
40
56
65
15
50
70
81
19
60
84
98
22
ns
ns
ns
4.5
Fig.14
SIGIN, COMPIN
to PC1OUT
tPZH/ tPZL 3-state output enable
time SIGIN, COMPIN
to PC2OUT
4.5
4.5
Fig.15
Fig.15
Fig.14
t
PHZ/ tPLZ 3-state output disable
time SIGIN, COMPIN
to PC2OUT
t
THL/ tTLH output transition time
7
ns
4.5
4.5
VI(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIGIN or COMPIN
15
mV
fi =
1 MHz
December 1990
18
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
OTHER
min. typ. max. typ. max. min. max.
∆f/T
frequency stability
with temperature
change
0.15
%/K 4.5 VI = VCOIN within
recommended
range;
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pf;
see Fig.16b
fo
VCO centre frequency 11.0 17.0
(duty factor = 50%)
MHz 4.5 VVCOIN = 1/2 VCC;
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF;
see Fig.17
∆fVCO
VCO frequency
linearity
0.4
50
%
%
4.5 R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF; see
Figs 18 and 19
δVCO
duty factor at VCOOUT
4.5
December 1990
19
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
FIGURE REFERENCES FOR DC CHARACTERISTICS
Fig.11 Input resistance at SIGIN, COMPIN with
∆VI = 0.5 V at self-bias point.
Fig.10 Typical input resistance curve at SIGIN,
COMPIN.
____ RS = 50 kΩ
- - - - RS = 300 kΩ
Fig.12 Input current at SIGIN, COMPIN with
Fig.13 Offset voltage at demodulator output as a
function of VCOIN and RS.
∆VI = 0.5 V at self-bias point.
December 1990
20
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
Fig.14 Waveforms showing input (SIGIN, COMPIN) to output (PC1OUT) propagation delays and the output
transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
Fig.15 Waveforms showing the 3-state enable and disable times for PC2OUT
.
December 1990
21
MSB711
MSB712
MSB710
25
25
25
handbook, halfpage
handbook, halfpage
handbook, halfpage
V
=
∆
CC
3 V
5 V
∆ f
(%)
∆ f
(%)
f
(%)
3 V
5 V
20
20
15
20
15
6 V
6 V
V
=
15
V
=
CC
CC
3 V
6 V
5 V
3 V
3 V
5 V
6 V
A
10
5
10
5
10
5
5 V
6 V
3 V
4.5 V
5 V
6 V
0
0
0
−5
−10
−15
−20
5
10
15
20
5
10
15
20
−25
−50
25
50
25
50
0
50
100
150
0
50
100
T
150
0
50
100
T
150
o
o
o
T
( C)
(
C)
(
C)
amb
amb
amb
(a)
(b)
(c)
Fig.16 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
without offset (R2 = ∞): (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ.
- - - - with offset (R1 = ∞): (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.
In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). This curve is set by the total VCO bias current, and is
not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; VVCO IN = 0.5 VCC
.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC WAVEFORMS
To obtain optimum temperature stability, C1 must be a small as possible, but larger than 100 pF.
Fig.16 Continued.
December 1990
23
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.17 Graphs showing VCO frequency (fVCO) as a function of the VCO input voltage (VVCOIN).
December 1990
24
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.18 Definition of VCO frequency linearity:
∆V = 0.5 V over the VCC range:
for VCO linearity
f1 + f2
f′0
=
--------------
2
Fig.19 Frequency linearity as a function of R1, C1
f′0 – f
linearity =
0 × 100%
----------------
and VCC: R2 = ∞ and ∆V = 0.5 V.
f′0
December 1990
25
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
____ C1 = 40 pF
____ C1 = 40 pF
- - - - C1 = 1 µF
- - - - C1 = 1 µF
Fig.20 Power dissipation versus the value of R1:
Fig.21 Power dissipation versus the value of R2:
CL = 50 pF; R1 = ∞; VVCOIN = GND = 0 V;
Tamb = 25 °C.
CL = 50 pF; R2 = ∞; VVCOIN = 1/2 VCC
Tamb = 25 °C.
;
Fig.22 Typical dc power dissipation of demodulator
section as a function of RS: R1 = R2 = ∞;
Tamb = 25 °C; VVCOIN = 1/2 VCC
.
December 1990
26
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046
in a phase-lock-loop system.
References should be made to Figs 27, 28 and 29 as indicated in the table.
Values of the selected components should be within the following ranges:
R1
R2
between 3 kΩ and 300 kΩ;
between 3 kΩ and 300 kΩ;
R1 + R2 parallel value > 2.7 kΩ;
C1
greater than 40 pF.
PHASE
COMPARATOR
SUBJECT
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
without extra
offset
PC1, PC2
With R2 = ∞ and R1 within the range 3 kΩ < R1 < 300 kΩ, the characteristics
of the VCO operation will be as shown in Fig. 23.
(Due to R1, C1 time constant a small offset remains when R2 = ∞.)
Fig. 23 Frequency characteristic of VCO operating without offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1 and C1
PC1
PC2
Given fo, determine the values of R1 and C1 using Fig.27.
Given fmax and fo, determine the values of R1 and C1 using Fig.27,
use Fig.29 to obtain 2fL and then use this to calculate fmin.
December 1990
27
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PHASE
COMPARATOR
SUBJECT
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
with extra
offset
PC1, PC2
With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ, 3 kΩ < R2 < 300 kΩ,
the characteristics of the VCO operation will be as shown in Fig. 24.
Fig. 24 Frequency characteristic of VCO operating with offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1, R2 and C1
PC1, PC2
Given f0 and fL, determine the value of product R1C1 by using Fig.29.
Calculate foff from the equation foff = fo − 1.6fL.
Obtain the values of C1 and R2 by using Fig.28.
Calculate the value of R1 from the value of C1 and the product R1C1.
December 1990
28
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PHASE
COMPARATOR
SUBJECT
DESIGN CONSIDERATIONS
PLL conditions
with no signal at
the SIGIN input
PC1
VCO adjusts to fo with φDEMOUT = 90° and VVCOIN = 1/2 VCC (see Fig.6).
VCO adjusts to fo with φDEMOUT = −360° and VVCOIN = min. (see Fig.8).
PC2
PLL frequency
capture range
PC1, PC2
Loop filter component selection
(a) τ = R3 x C2
(b) amplitude characteristic
(c) pole-zero diagram
Fig. 25 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
(a) τ1 = R3 x C2;
τ2 = R4 x C2;
(b) amplitude characteristic
(c) pole-zero diagram
τ3 = (R3 + R4) x C2
Fig. 26 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
PLL locks on
harmonics at
centre frequency
PC1
PC2
yes
no
noise rejection at PC1
high
low
signal input
PC2
AC ripple content PC1
when PLL is
locked
fr = 2fi, large ripple content at φDEMOUT = 90°
PC2
fr = fi, small ripple content at φDEMOUT = 0°
December 1990
29
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
(2) Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce
almost the same VCO output frequency.
Fig.27 Typical value of VCO centre frequency (fo) as a function of C1: R2 = ∞; VVCOIN = 1/2 VCC; INH = GND;
Tamb = 25 °C.
December 1990
30
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
(2) Interpolation for various values of R2 can be easily calculated because a constant R2C2 product will produce
almost the same VCO output frequency.
Fig.28 Typical value of frequency offset as a function of C1: R1 = ∞; VVCOIN = 1/2 VCC; INH = GND; Tamb = 25 °C.
December 1990
31
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.29 Typical frequency lock range (2fL) versus the product R1C1: VVCOIN range = 0.9 to (VCC − 0.9) V;
R2 = ∞; VCO gain:
2fL
KV
=
2 π (r/s/V).
------------------------------------
VVCOIN range
December 1990
32
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
on the application, the phase error can be defined as the
limit, a phase error of greater magnitude would be
considered out-of-lock. An example of an in-lock detection
circuit using the “7046A” is shown in Fig.30.
APPLICATION INFORMATION
Lock-detection circuit
The built-in lock-detection circuit will only work when used
in conjunction with the phase comparator PC2. The
lock-indication is derived from the phase error between
SIGIN and COMPIN. The PC2 has a typical phase error of
zero degrees over the entire VCO operating range.
However, to remain in-lock the circuit requires some small
adjustments. The variation is dependent on the loop
parameters and back-lash time (typically 5 ns). Depending
If the PLL is in-lock, only very small pulses will come from
the “up” or “down” connections of PC2. These pulses are
filtered out by a RC network. A Schmitt trigger produces a
steady state level, a HIGH level indicates an in-lock
condition and a pulsed output indicates an out-of-lock
condition as shown in Fig.31.
See Fig.31 for input waveform.
Fig.30 An example of an in-lock detection circuit using the “7046A”.
(a)
(b)
Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.
33
December 1990
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
CLD
tLD
=
=
capacitor connected to pin 15
(includes the parasitic input capacitance of the IC, approximately 3.5 pF).
phase difference between SIGIN and COMPIN (positive-going edges).
Fig.32 CLD capacitor value versus typical tLD
.
December 1990
34
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
The maximum permitted phase error
must be defined, before tLD can be
defined using the following formula:
φmax
1
tLD
=
×
.
----------- ------
360 f IN
Using this calculated value in Fig.32,
it is possible to define the value of
CLD, e.g. assuming the phase error is
36° and fIN = 2 MHz:
36°
360 2 MHz
1
t LD
=
×
= 50 ns,
--------- -----------------
and using Fig.32, it can be seen that
CLD is 26 pF.
Fig.33 Steady state signal for lock indication.
With the addition of one retriggerable
monostable (e.g. “123”, “423” or
“4538”) a steady state LOW and
HIGH indication can be obtained, as
shown in Fig.33.
December 1990
35
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
The characteristics equation is:
PLL design example
1 + H (s) × G (s) = 0.
The frequency synthesizer, used in the design example
shown in Fig.34, has the following parameters:
This results in:
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
1 + Kp × Kv × Kn × τ2
K p × K v × K n
s2 +
s +
= 0.
-------------------------------
-----------------------------------------------------
(τ1 + τ2)
(τ 1 + τ 2 )
settling time
overshoot
: 1 ms
: < 20%
The natural frequency ωn is defined as follows:
˙
The open-loop gain is H (s) x G (s) = Kp × Kf × Ko × Kn.
Kp × Kv × Kn
ωn
=
------------------------------- .
(τ1 + τ2)
Where:
Kp
Kf
=
=
=
=
phase comparator gain
low-pass filter transfer gain
Kv/s VCO gain
and the damping value ζ is defined as follows:
1 + Kp × Kv × Kn × τ2
1
ζ =
×
.
---------- -----------------------------------------------------
Ko
Kn
2 ω n τ1 + τ2
1/n divider ratio
The overshoot and settling time percentages are now used
to determine ωn. From Fig.35 it can be seen that the
damping ratio ζ = 0.8 will produce an overshoot of less
than 20% and settle to within 5% at ωnt = 4.5. The required
settling time is 1 ms. This results in:
The programmable counter ratio Kn can be found as
follows:
fout
2 MHz
---------------------
100 kHz
Nmin.
=
=
= 20
----------
fstep
5
--
t
5
ω n
=
=
= 5 × 103 r/s.
--------------
0.001
fout
3 MHz
---------------------
100 kHz
Nmax.
=
=
= 30
----------
fstep
Rewriting the equation for natural frequency results in:
Kp × Kv × Kn
The VCO is set by the values of R1, R2 and C1,
R2 = 10 kΩ (adjustable). The values can be determined
using the information in the section “DESIGN
CONSIDERATIONS”.
With fo = 2.5 MHz and fL = 500 kHz this gives the following
values (VCC = 5.0 V):
(τ1 + τ2) =
.
-------------------------------
2
ωn
The maximum overshoot occurs at Nmax.:
0.4 × 2 × 106
(τ 1 + τ 2 ) =
= 0.0011 s.
---------------------------------
50002 × 30
R1 = 10 kΩ
R2 = 10 kΩ
C1 = 500 pF
When C2 = 470 nF, then
(τ1 + τ2) × 2 × ωn × ζ – 1
The VCO gain is:
R4 =
= 790 Ω.
----------------------------------------------------------------
Kp × Kv × Kn
2fL × 2 × π
× 2 π ≈ 2 × 106 r/s/v
1 MHz
-----------------
3.2
KV
=
= =
----------------------------------------------
0.9 – (VCC – 0.9)
R3 is calculated using the damping ratio equation:
τ1
The gain of the phase comparator is:
VCC
R3 =
– R4 = 2 kΩ.
-------
C2
Kp
=
= 0.4 V/r.
------------
4 × π
The transfer gain of the filter is given by:
1 + τ2s
Kf =
------------------------------------
1 + (τ1 + τ2) s
Where:
τ 1 = R3C2 and τ2 = R4C2.
December 1990
36
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.34 Frequency synthesizer.
Note
For an extensive description and application example please refer to application note ordering number
9398 649 90011.
Also available a computer design program for PLL’s ordering number 9398 961 10061.
MGA959
1.6
−0.6
−0.4
−0.2
0
= 0.3
0.5
0.707
1.0
ζ
1.4
1.2
(t)
(t)
∆ Φ
e
∆ ω
e
∆ ω /ω
∆ Φ /ω
n
e
n
e
= 5.0
ζ
1.0
0.8
= 2.0
ζ
0.2
0.6
0.4
0.2
0.4
0.6
0.8
0
1.0
0
1
2
3
4
5
6
7
8
ω
t
n
Fig.35 Type 1, second order frequency step response.
Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with
an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method,
is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared
to the phase detector sampling rate but short compared to the PLL response time.
December 1990
37
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.36 Frequency compared to the time response.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
38
相关型号:
74HCT7080DB
IC HCT SERIES, 16-BIT PARITY GENERATOR/CHECKER, CONFIGURABLE OUTPUT, PDSO20, Arithmetic Circuit
NXP
74HCT7080N
IC HCT SERIES, 16-BIT PARITY GENERATOR/CHECKER, CONFIGURABLE OUTPUT, PDIP20, Arithmetic Circuit
NXP
74HCT7080PW-T
IC HCT SERIES, 16-BIT PARITY GENERATOR/CHECKER, CONFIGURABLE OUTPUT, PDSO20, Arithmetic Circuit
NXP
©2020 ICPDF网 联系我们和版权申明