74HCT74BQ,115 [NXP]
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger QFN 14-Pin;型号: | 74HCT74BQ,115 |
厂家: | NXP |
描述: | 74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger QFN 14-Pin 逻辑集成电路 触发器 |
文件: | 总21页 (文件大小:174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 4 — 27 August 2012
Product data sheet
1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
Input levels:
For 74HC74: CMOS level
For 74HCT74: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC74N
40 C to +125 C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT74N
74HC74D
40 C to +125 C
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT74D
74HC74DB
74HCT74DB
SSOP14
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 1.
Ordering information …continued
Type number Package
Temperature range Name
Description
Version
74HC74PW
74HCT74PW
74HC74BQ
74HCT74BQ
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
40 C to +125 C
DHVQFN14
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
4. Functional diagram
1SD
4
SD
1Q
1Q
1D
2
3
Q
Q
D
5
6
1CP
CP
FF
RD
4
3
2
1
4
10
S
5
6
1RD
2SD
1
C1
1SD 2SD
1D
R
10
SD
1Q
2Q
5
9
2
12
3
1D
2D
1CP
2CP
D
Q
Q
SD
2Q
2Q
2D
9
8
12
11
D
Q
Q
CP
10
11
12
13
11
S
FF
9
8
2CP
1Q
2Q
6
8
CP
C1
FF
RD
1D
R
RD
1RD 2RD
1 13
2RD
mna420
mna418
mna419
13
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
Q
C
C
C
C
C
C
C
C
D
Q
RD
SD
CP
mna421
C
C
Fig 4. Logic diagram for one flip-flop
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
2 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
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(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 5. Pin configuration for DIP14, SO14 and (T)SSOP14
Fig 6. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
Pin description
Pin
1
Description
asynchronous reset-direct input (active LOW)
data input
2
1CP
1SD
1Q
3
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
4
5
1Q
6
complement output
GND
2Q
7
ground (0 V)
8
complement output
2Q
9
output
2SD
2CP
2D
10
11
12
13
14
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
2RD
VCC
asynchronous reset-direct input (active LOW)
supply voltage
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
3 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
Table 3.
Function table[1]
Input
nSD
L
Output
nRD
H
nCP
X
nD
X
nQ
H
nQ
L
H
L
X
X
L
H
L
L
X
X
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 4.
Input
nSD
H
Function table[1]
Output
nRD
H
nCP
nD
L
nQn+1
nQn+1
L
H
L
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
25
+100
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
100
storage temperature
total power dissipation
65
+150
750
500
[1]
[1]
DIP14 package
-
-
mW
mW
SO14, (T)SSOP14 and DHVQFN14
packages
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
4 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC74
74HCT74
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
74HC74
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VIH or VIL
3.84
5.34
4.32
5.81
-
-
3.7
5.2
-
-
V
V
VOL
LOW-level
output voltage
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
0.15
0.16
-
0.33
0.33
1.0
-
-
-
0.4
0.4
V
V
II
input leakage
current
1.0
A
VCC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
40
-
80
A
input
3.5
pF
capacitance
74HCT74
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
input voltage
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
5 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 4 mA
3.84
4.32
-
3.7
-
V
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 4.0 mA
-
-
0.15
-
0.33
-
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
1.0
1.0
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
40
-
80
A
V
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; nD, nRD
inputs
-
-
70
80
315
360
-
-
343
392
A
A
pF
per input pin; nSD, nCP
input
CI
input
3.5
capacitance
[1] All typical values are measured at Tamb = 25 C.
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
6 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions
74HC74
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
[3]
tpd
propagation nCP to nQ, nQ; see
delay
Figure 7
VCC = 2.0 V
-
-
-
-
47
17
14
14
220
44
-
-
-
-
-
265
53
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
37
45
nSD to nQ, nQ; see
Figure 8
VCC = 2.0 V
-
-
-
-
50
18
15
14
250
50
-
-
-
-
-
300
60
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
43
51
nRD to nQ, nQ; see
Figure 8
VCC = 2.0 V
VCC = 4.5 V
-
-
-
-
52
19
16
15
250
50
-
-
-
-
-
300
60
-
ns
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
43
51
tt
transition
time
nQ, nQ; see Figure 7
VCC = 2.0 V
-
-
-
19
7
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width nCP HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
19
7
-
-
-
120
24
-
-
-
ns
ns
ns
17
6
20
nSD, nRD LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
19
7
-
-
-
120
24
-
-
-
ns
ns
ns
17
6
20
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 2.0 V
40
8
3
1
1
-
-
-
45
9
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
7
8
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
7 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
tsu
set-up time nD to nCP; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
75
15
13
6
2
2
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 6.0 V
th
hold time
nD to nCP; see Figure 7
VCC = 2.0 V
3
3
3
6
2
2
-
-
-
3
3
3
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
nCP; see Figure 7
VCC = 2.0 V
4.8
24
-
23
69
76
82
24
-
-
-
-
-
4.0
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
28
-
24
-
[4]
[2]
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
74HCT74
tpd
propagation nCP to nQ, nQ; see
delay
Figure 7
VCC = 4.5 V
-
-
18
15
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
[2]
[2]
[3]
nSD to nQ, nQ; see
Figure 8
VCC = 4.5 V
-
-
23
18
50
-
-
-
60
-
ns
ns
VCC = 5 V; CL = 15 pF
nRD to nQ, nQ; see
Figure 8
VCC = 4.5 V
-
-
24
18
50
-
-
-
60
-
ns
ns
VCC = 5 V; CL = 15 pF
nQ, nQ; see Figure 7
VCC = 4.5 V
tt
transition
time
-
7
9
19
-
-
22
-
ns
ns
tW
pulse width nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
23
27
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V
20
8
9
1
5
-
-
-
24
9
-
-
-
ns
ns
ns
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 4.5 V
tsu
set-up time nD to nCP; see Figure 7
VCC = 4.5 V
15
18
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
8 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
th
hold time
nD to nCP; see Figure 7
VCC = 4.5 V
3
3
-
3
-
ns
fmax
maximum
frequency
nCP; see Figure 7
VCC = 4.5 V
22
-
54
59
29
-
-
-
18
-
-
-
-
MHz
MHz
pF
VCC = 5 V; CL = 15 pF
[4]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC - 1.5 V
-
-
dissipation
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
.
.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
9 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
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Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Input to output propagation delay, output transition time, clock input pulse width and maximum
frequency
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
10 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
V
I
V
M
nCP input
GND
t
rec
V
I
V
M
nSD input
nRD input
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
nQ output
nQ output
V
V
M
V
OL
V
OH
M
V
OL
t
t
PLH
mna423
PHL
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Set and reset propogation delays, pulse widths and recovery time
Table 9.
Type
Measurement points
Input
VM
Output
VM
74HC74
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT74
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
11 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
Test
tr, tf
6 ns
6 ns
CL
RL
74HC74
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
tPLH, tPHL
tPLH, tPHL
74HCT74
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
12 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 10. Package outline SOT27-1 (DIP14)
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
13 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 11. Package outline SOT108-1 (SO14)
74HC_HCT74
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
14 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 12. Package outline SOT337-1 (SSOP14)
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
15 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 13. Package outline SOT402-1 (TSSOP14)
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
16 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 14. Package outline SOT762-1 (DHVQFN14)
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
17 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
13. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
74HC_HCT74 v.4
Modifications:
Release date Data sheet status
20120827 Product data sheet
Change notice
Supersedes
-
74HC_HCT74 v.3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT74 v.3
20030710
Product data sheet
-
74HC_HCT74_CNV v.2
74HC_HCT74_CNV v.2
19980223
Product specification
-
-
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
18 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
19 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
20 of 21
74HC74; 74HCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive edge-trigger
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 August 2012
Document identifier: 74HC_HCT74
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