74HCT85 概述
4-bit magnitude comparator 4位数值比较器
74HCT85 数据手册
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DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT85
4-bit magnitude comparator
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
weighted (A0 to A3 and B0 to B3), where A3 and B3 are the
most significant bits.
FEATURES
• Serial or parallel expansion without extra gating
• Magnitude comparison of any binary words
• Output capability: standard
The operation of the “85” is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
For proper compare operation the expander inputs (IA>B
IA=B and IA<B) to the least significant position must be
connected as follows: IA<B = IA>B = = LOW and
,
The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are
IA=B = HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs QA<B, QA>Β and QA=B to the
corresponding inputs of the significant comparator.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
An, Bn to QA>B, QA<B
An, Bn to QA=B
20
22
ns
18
15
11
20
15
15
3.5
20
ns
ns
ns
pF
pF
I
I
A<B,, IA=B, IA>B to QA<B, QA>B
A=B to QA=B
CI
input capacitance
3.5
18
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
2
IA<B
A < B expansion input
A = B expansion input
A > B expansion input
A > B output
3
IA=B
4
IA>B
5
QA>B
QA=B
QA<B
GND
B0 to B3
A0 to A3
VCC
6
A = B output
7
A < B output
8
ground (0 V)
9, 11, 14, 1,
10, 12, 13, 15
16
word B inputs
word A inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
Fig.4 Functional diagram.
APPLICATIONS
• Process controllers
• Servo-motor control
FUNCTION TABLE
COMPARING INPUTS
CASCADING INPUTS
OUTPUTS
A3, B3
A2, B2
A1, B1
A0, B0
IA>B
IA<B
IA=B
QA>B
QA<B
QA=B
A3>B3
A3<B3
A3=B3
A3=B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
L
L
L
L
A2>B2
A2<B2
H
A3=B3
A3=B3
A3=B3
A3=B3
A2=B2
A2=B2
A2=B2
A2=B2
A1>B1
A1<B1
A1=B1
A1=B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
L
L
L
L
A0>B0
A0<B0
H
A3=B3
A3=B3
A3=B3
A2=B2
A2=B2
A2=B2
A1=B1
A1=B1
A1=B1
A0=B0
A0=B0
A0=B0
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
H
A3=B3
A3=B3
A3=B3
A2=B2
A2=B2
A2=B2
A1=B1
A1=B1
A1=B1
A0=B0
A0=B0
A0=B0
X
H
L
X
H
L
H
L
L
L
L
H
L
L
H
H
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
VCC
+25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An, Bn to QA>B or QA<B
63
23
18
195
39
33
245
49
42
295
59
50
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
58
21
17
175
35
30
220
44
37
265
53
45
2.0 Fig.6
4.5
6.0
An, Bn to QA=B
PHL/ tPLH propagation delay
IA<B, IA=B, IA>B to
50
18
14
140
28
24
175
35
30
210
42
36
2.0 Fig.6
4.5
6.0
QA<B, QA>B
PHL/ tPLH propagation delay
39
14
11
120
24
20
150
30
26
180
36
31
2.0 Fig.6
4.5
6.0
I
A=B to QA=B
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.6
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
IA<B
IA>B
IA=B
An, Bn
1.00
1.00
1.50
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
VCC
+25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An, Bn to QA>B or QA<B
26
24
18
44
40
31
55
50
39
66
60
47
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
t
PHL/ tPLH propagation delay
An, Bn to QA=B
t
PHL/ tPLH propagation delay
I
A<B, IA=B, IA>B to
QA<B, QA>B
tPHL/ tPLH propagation delay
IA=B to QA=B
18
7
31
15
39
19
47
22
ns
ns
4.5 Fig.6
4.5 Fig.6
t
THL/ tTLH output transition time
December 1990
7
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the word A inputs (An), word B inputs (Bn) and expansion inputs (In) to the outputs
(Qn) propagation delays and the output transition times.
APPLICATION INFORMATION
Fig.7 Series cascading; comparing 12-bit words.
December 1990
8
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
Fig.8 Parallel cascading; comparing 12-bit words.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
9
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