74HCT9046AN,699_技术文档

74HCT9046A

PLL with band gap controlled VCO

Rev. 06 — 15 September 2009

Product data sheet

1. General description

The 74HCT9046A is a high-speed Si-gate CMOS device. It is speciﬁed in compliance with

JEDEC standard no 7A.

2. Features

I Operation power supply voltage range from 4.5 V to 5.5 V

I Low power consumption

I Inhibit control for ON/OFF keying and for low standby power consumption

I center frequency up to 17 MHz (typical) at V_CC= 5.5 V

I Choice of two phase comparators:

N PC1: EXCLUSIVE-OR

N PC2: Edge-triggered JK ﬂip-ﬂop

I No dead zone of PC2

I Charge pump output on PC2, whose current is set by an external resistor R_bias

I center frequency tolerance ±10 %

I Excellent Voltage Controlled Oscillator (VCO) linearity

I Low frequency drift with supply voltage and temperature variations

I On-chip band gap reference

I Glitch free operation of VCO, even at very low frequencies

I Zero voltage offset due to operational ampliﬁer buffering

I ESD protection:

N HBM JESD22-A114F exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

3. Applications

I FM modulation and demodulation where a small center frequency tolerance is

essential

I Frequency synthesis and multiplication where a low jitter is required (e.g. video

picture-in-picture)

I Frequency discrimination

I Tone decoding

I Data synchronization and conditioning

I Voltage-to-frequency conversion

I Motor-speed control

4. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74HCT9046AN

74HCT9046AD

−40 °C to +125 °C

DIP16

SO16

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

SOT109-1

plastic small outline package; 16 leads; body width

3.9 mm

74HCT9046APW −40 °C to +125 °C

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

2 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

5. Block diagram

f

out

C1

f

V

in

VCO_OUT

SIG_IN

COMP_IN

CC

16

C1A

C1B

7

6

4

3

14

9046A

PC1_OUT/

R2 12

R3

PHASE

COMPARATOR

1

PCP_OUT

2

R2

VCO

PC2_OUT

13

R1 11

PHASE

COMPARATOR

2

15 RB

R4

C2

R1

R

bias

5

10

9

8

1

DEM_OUT VCO_IN

GND

INH

R

s

mbd040

Fig 1. Block diagram

6. Functional diagram

PC1_OUT/

PCP_OUT

Φ

2

3

14

15

COMP_IN

SIG_IN

RB

PLL

9046A

Φ

PC1_OUT/

PCP_OUT

COMP_IN

3

2

PC2_OUT

VCO_OUT

13

14

SIG_IN

C1A

C1B

R1

13

PC2_OUT

6

7

C1A

6

7

C1B

R1

4

11

12

15

9

11

12

9

DEM_OUT

VCO_OUT

10

4

R2

VCO

R2

RB

VCO_IN

DEM_OUT

mbd038

10

VCO_IN

5

INH

5

INH

mbd039

Fig 2. Logic symbol

Fig 3. IEC logic symbol

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

3 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

7. Pinning information

7.1 Pinning

74HCT9046A

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

V

CC

PC1_OUT/

PCP_OUT

RB

COMP_IN

VCO_OUT

INH

SIG_IN

PC2_OUT

R2

C1A

R1

C1B

DEM_OUT

VCO_IN

GND

001aae500

Fig 5. Pin conﬁguration

7.2 Pin description

Table 2.

Symbol

GND

Pin description

1

Description

ground (0 V) of phase comparators

PC1_OUT/PCP_OUT

2

phase comparator 1 output or phase comparator pulse output

COMP_IN

VCO_OUT

INH

3

comparator input

4

VCO output

5

inhibit input

C1A

6

capacitor C1 connection A

capacitor C1 connection B

ground (0 V) VCO

C1B

7

GND

8

VCO_IN

DEM_OUT

R1

9

VCO input

10

11

12

13

14

15

16

demodulator output

resistor R1 connection

resistor R2 connection

phase comparator 2 output; current source adjustable with R_bias

signal input

R2

PC2_OUT

SIG_IN

RB

bias resistor (R_bias) connection

supply voltage

V_CC

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

5 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

8. Functional description

The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two

different phase comparators (PC1 and PC2) with a common signal input ampliﬁer and a

common comparator input, see Figure 1. The signal input can be directly coupled to large

voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage signals within the linear region

of the input ampliﬁers. With a passive low-pass ﬁlter, the 74HCT9046A forms a

second-order loop PLL.

The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However

extra features are built-in, allowing very high-performance phase-locked-loop applications.

This is done, at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is

equipped with a current source output stage here. Further a band gap is applied for all

internal references, allowing a small center frequency tolerance. The details are summed

up in Section 8.1. If one is familiar with the 74HCT4046A already, it will do to read this

section only.

8.1 Differences with respect to the familiar 74HCT4046A

• A center frequency tolerance of maximum ±10 %.

• The on board band gap sets the internal references resulting in a minimal frequency

shift at supply voltage variations and temperature variations.

• The value of the frequency offset is determined by an internal reference voltage of

2.5 V instead of V_CC− 0.7 V; In this way the offset frequency will not shift over the

supply voltage range.

• A current switch charge pump output on pin PC2_OUT allows a virtually ideal

performance of PC2; The gain of PC2 is independent of the voltage across the

low-pass ﬁlter; Further a passive low-pass ﬁlter in the loop achieves an active

performance. The inﬂuence of the parasitic capacitance of the PC2 output plays no

role here, resulting in a true correspondence of the output correction pulse and the

phase difference even up to phase differences as small as a few nanoseconds.

• Because of its linear performance without dead zone, higher impedance values for the

ﬁlter, hence lower C-values, can be chosen; correct operation will not be inﬂuenced by

parasitic capacitances as in case of the voltage source output using the

74HCT4046A.

• No PC3 on pin RB but instead a resistor connected to GND, which sets the

load/unload currents of the charge pump (PC2).

• Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz

and higher.

• Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to V_CC(no

bias resistor R_bias) pin PC1_OUT/PCP_OUT has its familiar function viz. output of

PC1. If at pin RB a resistor (R_bias) is connected to GND it is assumed that PC2 has

been chosen as phase comparator. Connection of R_biasis sensed by internal circuitry

and this changes the function of pin PC1_OUT/PCP_OUT into a lock detect output

(PCP_OUT) with the same characteristics as PCP_OUT of pin 1 of the 74HCT4046A.

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

6 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

• The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input

(pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For

the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to

minimize standby power consumption.

8.2 VCO

The VCO requires one external capacitor C1 (between pins C1A and C1B) and one

external resistor R1 (between pins R1 and GND) or two external resistors R1 and R2

(between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine

the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset

if required (see Figure 4).

The high input impedance of the VCO simpliﬁes the design of the low-pass ﬁlters by giving

the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass

ﬁlter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. The

DEM_OUT voltage equals that of the VCO input. If DEM_OUT is used, a series resistor

(R_s) should be connected from pin DEM_OUT to GND; if unused, DEM_OUT should be

left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator

input (pin COMP_IN), or connected via a frequency divider. The output signal has a duty

cycle of 50 % (maximum expected deviation 1 %), if the VCO input is held at a constant

DC level. A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator,

while a HIGH-level turns both off to minimize standby power consumption.

8.3 Phase comparators

The signal input (pin SIG_IN) can be directly coupled to the self-biasing ampliﬁer at

pin SIG_IN, provided that the signal swing is between the standard HC family input logic

levels. Capacitive coupling is required for signals with smaller swings.

8.3.1 Phase Comparator 1 (PC1)

This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies

(f_i) must have a 50 % duty cycle to obtain the maximum locking range. The transfer

characteristic of PC1, assuming ripple (f_r= 2f_i) is suppressed, is:

V

V_{DEM_OUT}

=

^CC(Φ

– Φ_{COMP_IN})

SIG_IN

----------

π

where:

V_{DEM_OUT}is the demodulator output at pin DEM_OUT

V_{DEM_OUT}= V_{PC1_OUT}(via low-pass)

V

The phase comparator gain is: K_p

=

^CC(V ⁄ r)

----------

π

The average output voltage from PC1, fed to the VCO input via the low-pass ﬁlter and

seen at the demodulator output at pin DEM_OUT (V_{DEM_OUT}), is the resultant of the phase

differences of signals (SIG_IN) and the comparator input (COMP_IN) as shown in

Figure 6. The average of V_{DEM_OUT}is equal to 0.5V_CCwhen there is no signal or noise at

SIG_IN and with this input the VCO oscillates at the center frequency (f₀). Typical

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

waveforms for the PC1 loop locked at f₀are shown in Figure 7. This ﬁgure also shows the

actual waveforms across the VCO capacitor at pins C1A and C1B (V_C1Aand V_C1B) to

show the relation between these ramps and the VCO_OUT voltage.

The frequency capture range (2f₀) is deﬁned as the frequency range of input signals on

which the PLL will lock if it was initially out-of-lock. The frequency lock range (2f_L) is

deﬁned as the frequency range of the input signals on which the loop will stay locked if it

was initially in lock. The capture range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass ﬁlter characteristics and can be

made as large as the lock range. This conﬁguration remains locked even with very noisy

input signals. Typical behavior of this type of phase comparator is that it may lock to input

frequencies close to the harmonics of the VCO center frequency.

mbd101

V

CC

V

DEM_OUT(AV)

0.5V

CC

0

o

0

90

180

Φ

PC_IN

V

V_{DEM_OUT}= V_{PCI_OUT}

=

^CCΦ_{SIG_IN}– Φ_{COMP_IN}

----------

π

Φ_{PC_IN}= (Φ_{SIG_IN}– Φ_{COMP_IN}

)

Fig 6. Phase comparator 1; average output voltage as a function of input phase

difference

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

SIGN_IN

COMP_IN

VCO_OUT

PC1_OUT

VCO_IN

V

CC

GND

C1A

V

C1A

C1B

mbd100

Fig 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f₀

8.3.2 Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency detector. When the PLL is using

this comparator, the loop is controlled by positive signal transitions and the duty cycles of

SIG_IN and COMP_IN are not important. PC2 comprises two D-type ﬂip-ﬂops, control

gating and a 3-state output stage with sink and source transistors acting as current

sources, henceforth called charge pump output of PC2. The circuit functions as an

up-down counter (see Figure 4) where SIG_IN causes an up-count and COMP_IN a down

count. The current switch charge pump output allows a virtually ideal performance of PC2,

due to appliance of some pulse overlap of the up and down signals, see Figure 8a.

The pump current I_cpis independent from the supply voltage and is set by the internal

band gap reference of 2.5 V.

2.5

R_bias

I_cp= 17 ×

(A)

-----------

Where R_biasis the external bias resistor between pin RB and ground.

The current and voltage transfer function of PC2 are shown in Figure 9.

The phase comparator gain is:

I_cp

K_P

=

(A ⁄ r)

---------

2π

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

V

CC

up

I

cp

V

CC

PC2_OUT

C2

up

PC2_OUT

VC2_OUT

R3'

down

I

cp

down

C2

∆ Φ = Φ_{PC_IN}

pulse overlap of

approximately 15 ns

mbd046

mbd099

a. At every ∆Φ, even at zero ∆Φ both switches are

closed simultaneously for a short period (typically

15 ns).

b. Comparable voltage-controlled switch

Fig 8. The current switch charge pump output of PC2

+I

cp

V

CC

V

DEM_OUT(AV)

I

× R

cp

0

0.5V

CC

−I

cp

−2

π

+2

π

0

−2

Φ

PC_IN

+2

π

0

π

Φ

001aak442

PC_IN

001aak443

a. Current transfer

b. Voltage transfer. This transfer can be observed at

PC2_OUT by connecting a resistor (R = 10 kΩ)

between PC2_OUT and 0.5V_CC

.

I_cp

5

V_{DEM_OUT}= V_{PC2_OUT}

=

Φ

------

pump current

Φ

PC_IN

---------

PC_IN

4π

Φ_{PC_IN}= (Φ_{SIG_IN}– Φ_{COMP_IN}

Fig 9. Phase comparator 2 current and voltage transfer characteristics

2π

)

When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads

that of COMP_IN, the up output driver at PC2_OUT is held ‘ON’ for a time corresponding

to the phase difference (Φ_{PC_IN}). When the phase of SIG_IN lags that of COMP_IN, the

down or sink driver is held ‘ON’.

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is

held ‘ON’ for most of the input signal cycle time and for the remainder of the cycle time

both drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN

frequency, then it is the sink driver that is held ‘ON’ for most of the cycle. Subsequently the

voltage at the capacitor (C2) of the low-pass ﬁlter connected to PC2_OUT varies until the

signal and comparator inputs are equal in both phase and frequency. At this stable point

the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at

pin 9 is a high-impedance. Also in this condition the signal at the phase comparator pulse

output (PCP_OUT) has a minimum output pulse width equal to the overlap time, so can be

used for indicating a locked condition.

Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full

frequency range of the VCO. Moreover, the power dissipation due to the low-pass ﬁlter is

reduced because both output drivers are OFF for most of the signal input cycle. It should

be noted that the PLL lock range for this type of phase comparator is equal to the capture

range and is independent of the low-pass ﬁlter. With no signal present at SIG_IN the VCO

adjust, via PC2, to its lowest frequency.

By using current sources as charge pump output on PC2, the dead zone or backlash time

could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance

plays no role here. This enables a linear transfer function, even in the vicinity of the zero

crossing. The differences between a voltage switch charge pump and a current switch

charge pump are shown in Figure 11.

SIG_IN

COMP_IN

VCO_OUT

15 ns typical

UP

PC_IN

DOWN

CURRENT AT

PC2_OUT

high-impedance OFF-state,

(zero current)

PC2_OUT/VCO_IN

PCP_OUT

mbd047

The pulse overlap of the up and down signals (typically 15 ns).

Fig 10. Timing diagram for PC2

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Product data sheet

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

2.75

VCO_IN

(1)

2.50

(1)

2.50

(2)

0

2.25

−25

25

−25

0

25

phase error (ns)

001aak444

001aak445

(1) Due to parasitic capacitance on PC2_OUT.

(2) Backlash time (dead zone).

a. Response with traditional voltage-switch

charge-pump PC2_OUT (74HCT4046A).

b. Response with current switch charge-pump

PC2_OUT as applied in the 74HCT9046A.

Fig 11. The response of a locked-loop in the vicinity of the zero crossing of the phase error

The design of the low-pass ﬁlter is somewhat different when using current sources. The

external resistor R3 is no longer present when using PC2 as phase comparator.

The current source is set by R_bias. A simple capacitor behaves as an ideal integrator now,

because the capacitor is charged by a constant current. The transfer function of the

voltage switch charge pump may be used. In fact it is even more valid, because the

transfer function is no longer restricted for small changes only. Further the current is

independent from both the supply voltage and the voltage across the ﬁlter. For one that is

familiar with the low-pass ﬁlter design of the 74HCT4046A a relation may show how R_bias

relates with a ﬁctive series resistance, called R3'.

This relation can be derived by assuming ﬁrst that a voltage controlled switch PC2 of the

74HCT4046A is connected to the ﬁlter capacitance C2 via this ﬁctive R3' (see Figure 8b).

Then during the PC2 output pulse the charge current equals:

V_CC– V_C2(0)

I_cp

=

--------------------------------

R3'

2.5

With the initial voltage V_C2(0)at: 0.5V_CC= 2.5 V, I_cp= -------

R3'

As shown before the charge current of the current switch of the 74HCT9046A is:

2.5

R_bias

I_cp= 17 ×

-----------

Hence:

R

R3‘ = ^bias(Ω)

-----------

17

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

Using this equivalent resistance R3' for the ﬁlter design the voltage can now be expressed

as a transfer function of PC2; assuming ripple (f_r= f_i) is suppressed, as:

5

4π

K_PC2

=

(V ⁄ r)

------

Again this illustrates the supply voltage independent behavior of PC2.

8.4 Loop ﬁlter component selection

Examples of PC2 combined with a passive ﬁlter are shown in Figure 12 and 13. Figure 12

shows that PC2 with only a C2 ﬁlter behaves as a high-gain ﬁlter. For stability the damped

version of Figure 13 with series resistance R4 is preferred.

Practical design values for R_biasare between 25 kΩ and 250 kΩ with R3' = 1.5 kΩ

to 15 kΩ for the ﬁlter design. Higher values for R3' require lower values for the ﬁlter

capacitance which is very advantageous at low values of the loop natural frequency ω_n.

A

I

cp

F

(jω)

I

cp

17

−1/

Aτ

1

C2

INPUT

OUTPUT

001aak449

R

bias

ω

1/

Aτ

1

001aak450

001aak451

a. Simple loop ﬁlter for PC2

without damping

b. Amplitude characteristic

c. Pole zero diagram

A = DC gain limit, due to leakage

R

1

τ₁

=

^bias× C2 = R3' × C2

F_{( jω)}

=

≈

----------------------------- -----------

-----------

1 ⁄ A + jωτ₁jωτ₁

17

Fig 12. Simple loop ﬁlter for PC2 without damping

74HCT9046A_6

Product data sheet

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

A

I

F

cp

(jω)

I

cp

17

1/

O

Aτ

1

R4

C2

−1/

τ

INPUT

OUTPUT

001aak446

2

R

m

bias

ω

1/

1 /

Aτ

2

1

001aak447

001aak448

a. Simple loop ﬁlter for PC2 with

damping

b. Amplitude characteristic

c. Pole zero diagram

A = DC gain limit, due to leakage

R

1 + jωτ₂

^bias× C2 = R3‘ × C2

F_(jω)

=

-----------------------------

τ₁

=

-----------

17

τ₂= R4 × C2

1 ⁄ A + jωτ₁

Fig 13. Simple loop ﬁlter for PC2 with damping

9. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

−0.5

input clamping current

output clamping current

output current

V_I< −0.5 V or V_I> V_CC+ 0.5 V

V_O< −0.5 V or V_O> V_CC+ 0.5 V

−0.5 V < V_O< V_CC+ 0.5 V

-

±20

±25

+50

-

mA

°C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

−50

−65

storage temperature

total power dissipation

DIP16

+150

T_amb= −40 °C to +125 °C

[1]

[2]

-

750

500

mW

SO16 and TSSOP16

[1] For DIP16 packages: above 70 °C the value of P_totderates linearly with 12 mW/K.

[2] For SO16 and TSSOP16 packages: above 70 °C the value of P_totderates linearly with 8 mW/K.

74HCT9046A_6

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Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

10. Recommended operating conditions

Table 4.

Symbol

V_CC

Operating conditions

Parameter

Conditions

Min

4.5

0

Typ

Max

5.5

Unit

V

supply voltage

5.0

V_I

input voltage

-

V_CC

+125

139

V

V_O

output voltage

0

V

T_amb

∆t/∆V

ambient temperature

input transition rise and fall rate

−40

-

°C

ns/V

pin INH; V_CC= 4.5 V

1.67

11. Static characteristics

Table 5.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max Unit

T_amb= 25 °C

Phase comparator section

V_IH

HIGH-level input voltage

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

3.15 2.4

-

V

V_IL

LOW-level input voltage

HIGH-level output voltage

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

-

2.1

1.35

V_OH

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= −20 µA

4.4

4.5

-

V

I_O= −4.0 mA

3.98 4.32

V_OL

LOW-level output voltage

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= 20 µA

-

0

0.1

V

I_O= 4.0 mA

0.15 0.26

V

I_I

input leakage current

pins SIG_IN and COMP_IN;

V_CC= 5.5 V; V_I= V_CCor GND

-

±30

µA

I_OZ

R_I

OFF-state output current

input resistance

pin PC2_OUT; V_CC= 5.5 V;

V_I= V_IHor V_IL; V_O= V_CCor GND

-

±0.5 µA

SIG_IN and COMP_IN;

250

-

kΩ

V_CC= 4.5 V; V_Iat self-bias

operating point; ∆V_I= 0.5 V;

see Figure 14, 15 and 16

R_bias

bias resistance

V_CC= 4.5 V

25

-

250

kΩ

I_cp

charge pump current

V_CC= 4.5 V; R_bias= 40 kΩ

±0.53 ±1.06 ±2.12 mA

VCO section

V_IH

HIGH-level input voltage

LOW-level input voltage

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

2.0

-

1.6

1.2

-

V

V_IL

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

0.8

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

15 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

Table 5.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_OH

HIGH-level output voltage

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= −20 µA

4.4

4.5

-

V

I_O= −4.0 mA

3.98 4.32

V_OL

LOW-level output voltage

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= 20 µA

-

0

0.1

V

I_O= 4.0 mA

0.15 0.26

pins C1A and C1B; V_CC= 4.5 V;

V_I= V_IHor V_IL; I_O= 4.0 mA

-

0.40

I_I

input leakage current

pins INH and VCO_IN;

-

±0.1 µA

V_CC= 5.5 V; V_I= V_CCor GND

R1

R2

C1

resistor 1

resistor 2

capacitor 1

V_CC= 4.5 V

3

-

300

kΩ

pF

3

40

no

limit

V_{VCO_IN}

voltage on pin VCO_IN

over the range speciﬁed for R1

V_CC= 4.5 V

1.1

-

3.4

3.9

4.4

V

V_CC= 5.0 V

V_CC= 5.5 V

Demodulator section

R_s

series resistance

V_CC= 4.5 V; at R_s> 300 kΩ the

leakage current can inﬂuence

V_{DEM_OUT}

50

-

300

kΩ

mV

Ω

V_offset

offset voltage

VCO_IN to V_{DEM_OUT}; V_CC= 4.5 V;

V_I= V_{VCO_IN}= 0.5V_CC; values

taken over R_srange; see Figure 17

±20

25

-

R_dyn

dynamic resistance

DEM_OUT; V_CC= 4.5 V;

-

V_{DEM_OUT}= 0.5V_CC

General

I_CC

supply current

disabled; V_CC= 5.5 V;

pin INH at V_CC

-

8.0

360

-

µA

pF

∆I_CC

additional supply current

input capacitance

pin INH; V_I= V_CC− 2.1 V; V_CC

4.5 V; other inputs at V_CCor GND;

=

100

3.5

C_I

T_amb= −40 °C to +85 °C

Phase comparator section

V_IH

HIGH-level input voltage

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

3.15

-

V

V_IL

LOW-level input voltage

1.35

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

16 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

Table 5.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_OH

HIGH-level output voltage

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= −20 µA

4.4

-

V

I_O= −4.0 mA

3.84

V_OL

LOW-level output voltage

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= 20 µA

-

0.1

V

I_O= 4.0 mA

0.33

±38

V

I_I

input leakage current

SIG_IN and COMP_IN;

µA

V_CC= 5.5 V; V_I= V_CCor GND

I_OZ

OFF-state output current

PC2_OUT; V_CC= 5.5 V;

-

±5.0 µA

V_I= V_IHor V_IL; V_O= V_CCor GND

VCO section

V_IH

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

2.0

-

V

V_IL

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

0.8

V_OH

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= −20 µA

4.4

-

V

I_O= −4.0 mA

3.84

V_OL

LOW-level output voltage

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= 20 µA

-

0.1

V

I_O= 4.0 mA

0.33

0.47

pins C1A and C1B; V_CC= 4.5 V;

V_I= V_IHor V_IL; I_O= 4.0 mA

I_I

input leakage current

pins INH and VCO_IN;

-

±1.0 µA

V_CC= 5.5 V; V_I= V_CCor GND

General

I_CC

supply current

disabled; V_CC= 5.5 V;

pin INH at V_CC

-

80.0 µA

∆I_CC

additional supply current

per input pin; V_I= V_CC− 2.1 V;

450

µA

V_CC= 4.5 V; other inputs at V_CCor

GND;

T_amb= −40 °C to +125 °C

Phase comparator section

V_IH

HIGH-level input voltage

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

pins SIG_IN and COMP_IN;

V_CC= 4.5 V; DC coupled

3.15

-

V

V_IL

LOW-level input voltage

1.35

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

17 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

Table 5.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_OH

HIGH-level output voltage

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= −20 µA

4.4

3.7

-

V

I_O= −4.0 mA

V_OL

LOW-level output voltage

pins PCP_OUT and PCn_OUT;

V_CC= 4.5 V; V_I= V_IHor V_IL

I_O= 20 µA

-

0.1

0.4

±45

V

I_O= 4.0 mA

V

I_I

input leakage current

pins SIG_IN and COMP_IN;

V_CC= 5.5 V; V_I= V_CCor GND

µA

I_OZ

OFF-state output current

pin PC2_OUT; V_CC= 5.5 V;

-

±10.0 µA

V_I= V_IHor V_IL; V_O= V_CCor GND

VCO section

V_IH

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

2.0

-

V

V_IL

pin INH; V_CC= 4.5 V to 5.5 V;

DC coupled

0.8

V_OH

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= −20 µA

4.4

3.7

-

V

I_O= −4.0 mA

V_OL

LOW-level output voltage

pin VCO_OUT; V_CC= 4.5 V;

V_I= V_IHor V_IL

I_O= 20 µA

-

0.1

V

I_O= 4.0 mA

0.4

pins C1A and C1B; V_CC= 4.5 V;

V_I= V_IHor V_IL; I_O= 4.0 mA

0.54

I_I

input leakage current

pins INH and VCO_IN;

-

±1.0 µA

V_CC= 5.5 V; V_CCor GND

General

I_CC

supply current

disabled; V_CC= 5.5 V;

pin INH at V_CC

-

160.0 µA

∆I_CC

additional supply current

per input pin; V_I= V_CC− 2.1 V;

490

µA

V_CC= 4.5 V; other inputs at V_CCor

GND;

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

18 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mga956 - 1

mbd108

800

I

R

(kΩ)

∆V

I

600

400

200

0

V

=

CC

4.5 V

self-bias operating point

5.5 V

(0.5 V ) − 0.25

0.5 V

(0.5 V ) + 0.25

CC

V

V (V)

I

Fig 14. Typical input resistance curve at SIG_IN and

COMP_IN

Fig 15. Input resistance at SIG_IN; COMP_IN with

∆V_I= 0.5 V at self-bias point

mga958

mga957

60

5

V

= 5.5V

V

offset

CC

(mV)

40

4.5 V

I

(µA)

20

V

= 4.5 V

CC

0

−20

−40

4.5 V

5.5 V

−5

(0.5 V ) − 0.25

(0.5 V ) − 2

0.5 V

(0.5 V ) + 2

CC

(V)

CC

V

0.5 V

(0.5 V ) + 0.25

CC

VCO_IN

V (V)

I

___ R_s= 50 kΩ

- - - R_s= 300 kΩ

Fig 16. Input current at SIG_IN; COMP_IN with

Fig 17. Offset voltage at demodulator output as a

function of VCO_IN and R_s

∆V_I= 0.5 V at self-bias point

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

19 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

12. Dynamic characteristics

Table 6.

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF.

Dynamic characteristics^[1]

Symbol

Parameter

Conditions

Min

Typ

Max Unit

T_amb= 25 °C

Phase comparator section

t_pd

propagation delay

SIG_IN, COMP_IN to PC1_OUT;

V_CC= 4.5 V; see Figure 18

-

23

35

40

68

ns

SIG_IN, COMP_IN to PCP_OUT;

V

_CC= 4.5 V; see Figure 18

SIG_IN, COMP_IN to PC2_OUT;

_CC= 4.5 V; see Figure 19

SIG_IN, COMP_IN to PC2_OUT;

_CC= 4.5 V; see Figure 19

t_en

enable time

disable time

-

30

36

56

65

ns

V

t_dis

V

t_t

transition time

V_CC= 4.5 V; see Figure 18

-

7

15

-

ns

[4]

[5]

V_i(p-p)

peak-to-peak input voltage

pin SIGN_IN or COMP_IN;

50

mV

V

_CC= 4.5 V; AC coupled; f_i= 1 MHz

VCO section

∆f

frequency deviation

center frequency

V_CC= 5.0 V; V_{VCO_IN}= 3.9 V;

R1 = 10 kΩ; R2 = 10 kΩ; C1 = 1 nF

−10

-

+10

-

%

f₀

V_CC= 4.5 V; duty cycle = 50 %;

11.0 15.0

MHz

V

_{VCO_IN}= 0.5V_CC; R1 = 4.3 kΩ;

R2 = ∞ Ω; C1 = 40 pF; see Figure 23

and 31

V

_CC= 5 V; duty cycle = 50 %;

_{VCO_IN}= 0.5V_CC; R1 = 3 kΩ;

-

16.0

-

MHz

R2 = ∞ Ω; C1 = 40 pF; see Figure 23

and 31

[6]

∆f/f

relative frequency variation

duty cycle

V

_CC= 4.5 V; R1 = 100 kΩ; R2 = ∞ Ω;

-

0.4

50

-

%

C1 = 100 pF; see Figure 24 and 25

δ

VCO_OUT; V_CC= 4.5 V

General

C_PD

[2][3]

power dissipation capacitance

-

20

-

pF

T_amb= −40 °C to +85 °C

Phase comparator section

t_pd

propagation delay

SIG_IN, COMP_IN to PC1_OUT;

V_CC= 4.5 V; see Figure 18

-

50

85

ns

SIG_IN, COMP_IN to PCP_OUT;

V

_CC= 4.5 V; see Figure 18

SIG_IN, COMP_IN to PC2_OUT;

_CC= 4.5 V; see Figure 19

SIG_IN, COMP_IN to PC2_OUT;

_CC= 4.5 V; see Figure 19

t_en

enable time

disable time

transition time

-

70

81

19

ns

V

t_dis

V

t_t

V_CC= 4.5 V; see Figure 18

VCO section

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

20 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

Table 6.

Dynamic characteristics^[1]…continued

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

[7]

∆f/∆T

frequency variation with

temperature

V_CC= 4.5 V; V_{VCO_IN}= 0.5V_CC

;

-

0.06

-

%/K

recommended range: R1 = 10 kΩ;

R2 = 10 kΩ; C1 = 1 nF; see Figure 20,

21 and 22

T

_amb= −40 °C to +125 °C

Phase comparator section

t_pd

propagation delay

SIG_IN, COMP_IN to PC1_OUT;

V_CC= 4.5 V; see Figure 18

-

60

ns

SIG_IN, COMP_IN to PCP_OUT;

102

V

_CC= 4.5 V; see Figure 18

SIG_IN, COMP_IN to PC2_OUT;

_CC= 4.5 V; see Figure 19

t_en

enable time

disable time

-

84

98

ns

V

t_dis

SIG_IN, COMP_IN to PC2_OUT;

V_CC= 4.5 V; see Figure 19

V_CC= 4.5 V; see Figure 18

t_t

transition time

-

22

ns

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH; t_tis the same as t_TLHand t_THL

.

[2] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = total load switching outputs;

∑(C_L× V_CC²× f_o) = sum of outputs.

[3] Applies to the phase comparator section only (pin INH = HIGH). For power dissipation of the VCO and demodulator sections, see

Figure 26, 27 and 28.

[4] This is the (peak to peak) input sensitivity.

[5] This is the center frequency tolerance.

[6] This is the frequency linearity.

[7] This is the frequency stability with temperature change.

V

SIG_IN, COMP_IN

inputs

M

t

PLH

PHL

PCP_OUT, PC1_OUT

outputs

V

M

t

THL

TLH

mbd106

V_M= 0.5V_CC; V_I= GND to V_CC

.

Fig 18. Waveforms showing input (SIG_IN and COMP_IN) to output (PCP_OUT and PC1_OUT) propagation

delays and the output transition times

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

21 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

SIG_IN

input

V

M

COMP_IN

input

V

M

t

PLZ

PHZ

t

PZL

PZH

90%

PC2_OUT

output

V

M

10%

mga941

V_M= 0.5V_CC; V_I= GND to V_CC

.

Fig 19. Waveforms showing the enable and disable times for PC2_OUT

mbd116

mbd115

15

10

5

20

∆ f

(%)

∆ f

(%)

10

0

−10

−20

0

V

=

CC

−5

V

=

CC

5.5 V

4.5 V

5.5 V

4.5 V

−10

−15

−50

0

50

100

T

150

−50

0

50

100

T

150

(°C)

amb

a. R1 = 3 kΩ; R2 = ∞ Ω; C1 = 100 pF.

b. R1 = 10 kΩ; R2 = ∞ Ω; C1 = 100 pF.

Fig 20. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

22 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd124

5.5 V

mbd117

10

15

10

5

V

=

CC

∆ f

(%)

∆ f

(%)

4.5 V

5

0

V

=

CC

0

5.5 V

−5

−10

−15

−5

4.5 V

−10

−20

−50

0

50

100

150

−50

0

50

100

150

T

(°C)

Tamb (°C)

amb

a. R1 = 300 kΩ; R2 = ∞ Ω; C1 = 100 pF.

b. R1 = ∞ Ω; R2 = 3 kΩ; C1 = 100 pF.

Fig 21. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

mbd119

mbd118

10

∆ f

(%)

8

4

0

∆ f

(%)

5

0

V

=

−4

−8

CC

V

=

CC

4.5 V

5.5 V

−5

5.5 V

4.5 V

−10

−12

−50

0

50

100

150

−50

0

50

100

T

150

T

(°C)

amb

a. R1 = ∞ Ω; R2 = 10 kΩ; C1 = 100 pF.

b. R1 = ∞ Ω; R2 = 300 kΩ; C1 = 100 pF.

Fig 22. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

23 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd112

mbd113

30

20

10

0

f

VCO

(MHz)

(kHz)

V

=

CC

4.5 V

5.5 V

20

V

=

CC

4.5 V

10

5.5 V

0

2

4

6

0

2

4

6

V

(V)

V

(V)

VCO_IN

a. R1 = 4.3 kΩ; C1 = 39 pF.

b. R1 = 4.3 kΩ; C1 = 100 nF.

mbd111

mbd120

400

800

f

VCO

(Hz)

300

(kHz)

600

V

= 5.5 V

CC

V

= 5.5 V

CC

4.5 V

frequency

4.5 V

frequency

200

100

0

400

200

0

2

4

6

0

2

4

6

V

(V)

V

(V)

VCO_IN

c. R1 = 300 kΩ; C1 = 39 pF.

d. R1 = 300 kΩ; C1 = 100 nF.

Fig 23. Graphs showing VCO frequency as a function of the VCO input voltage (V_{VCO_IN}

)

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

24 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd114

4

0

C1 = 1 µF

4.5 V

5.5 V

f_VCO

mga937

(%)

f

(MHz)

C1 =

39 pF

f

2

4.5 V

f

0

f'

0

−4

−8

f

1

5.5 V

V

min

max

0.5 V

CC

2

3

1

10

R1 (kΩ)

V

(V)

VCO_IN

R2 = ∞ Ω and ∆V = 0.5 V

f ₁+ f ₂

f‘₀

=

-----------------

2

f‘₀– f

linearity =

⁰× 100 %

-----------------

f ₀

Fig 24. Deﬁnition of VCO frequency linearity:

Fig 25. Frequency linearity as a function of R1, C1 and

V_CC

∆V = 0.5 V over the V_CCrange

mbd110

mbd121

1

V

=

CC

V

=

CC

P

D

5.5 V

C1 = 39 pF

5.5 V

C1 = 1 µF

(W)

4.5 V

C1 = 1 µF

4.5 V

C1 = 39 pF

1

10

5.5 V

C1 = 39 pF

5.5 V

4.5 V

C1 = 1 µF

C1 = 39 pF

2

10

0

100

200

300

0

100

200

300

R2 (kΩ)

R1 (kΩ)

R2 = ∞ Ω

R1 = ∞ Ω

Fig 26. Power dissipation as a function of R1

Fig 27. Power dissipation as a function of R2

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

25 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd109

3

4

5

10

P

DEM

(W)

V

=

CC

4.5 V

5.5 V

10

2

3

10

R

s

(kΩ)

Fig 28. Typical power dissipation as a function of R_s

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

26 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

13. Application information

This information is a guide for the approximation of values of external components to be

used with the 74HCT9046A in a phase-locked-loop system.

Values of the selected components should be within the ranges shown in Table 7.

Table 7.

Component

R1

Survey of components

Value

between 3 kΩ and 300 kΩ

parallel value > 2.7 kΩ

> 40 pF

R2

R1 + R2

C1

Table 8.

Subject

Design considerations for VCO section

Phase comparator

Design consideration

VCO frequency

without extra

offset

PC1, PC2

VCO frequency characteristic. With R2 = ∞ and R1 within the range

3 kΩ < R1 < 300 kΩ, the characteristics of the VCO operation will be as

shown in Figure 29a. (Due to R1, C1 time constant a small offset remains

when R2 = ∞ Ω).

PC1

Selection of R1 and C1. Given f₀, determine the values of R1 and C1 using

Figure 31.

PC2

Given f_maxand f₀determine the values of R1 and C1 using Figure 31; use

Figure 33 to obtain 2f_Land then use this to calculate f_min

.

VCO frequency

with extra offset

PC1, PC2

VCO frequency characteristic. With R1 and R2 within the ranges

3 kΩ < R1 < 300 kΩ < R2 < 300 kΩ, the characteristics of the VCO

operation is as shown in Figure 29b.

PC1, PC2

Selection of R1, R2 and C1. Given f₀and f_Ldetermine the value of product

R1C1 by using Figure 33. Calculate f_offfrom the equation f_off= f₀− 1.6f_L.

Obtain the values of C1 and R2 by using Figure 32. Calculate the value of

R1 from the value of C1 and the product R1C1.

PLL conditions with PC1

VCO adjusts to f₀with Φ_{PC_IN}= 90° and V_{VCO_IN}= 0.5V_CC

no signal at pin

SIG_IN

PC2

VCO adjusts to f_offsetwith Φ_{PC_IN}= −360° and V_{VCO_IN}= minimum

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mga938

f

VCO

f

max

f

0

2f

due to

L

R1,C1

f

min

1.1 V

0.5 V

V

−1.1 V

CC

V

CC

VCO_IN

a. Operating without offset; f₀= center frequency; 2f_L= frequency lock range.

mga939

f

VCO

f

max

f

0

due to

R1,C1

2f

L

f

min

f

off

0.6f

L

due to

R2,C1

0.5 V

V

−1.1 V

CC

V

CC

1.1 V

CC

VCO_IN

b. Operating with offset; f₀= center frequency; 2f_L= frequency lock range.

Fig 29. Frequency characteristic of VCO

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

13.1 Filter design considerations for PC1 and PC2 of the 74HCT9046A

Figure 30 shows some examples of passive and active ﬁlters to be used with the phase

comparators of the 74HCT9046A. Transfer functions of phase comparators and ﬁlters are

given in Table 9.

Table 9.

Transfer functions of phase comparators and ﬁlters

Phase

Explanation

Figure

Filter type

Transfer function

comparator

PC1

Figure 30a

passive ﬁlter without

damping

V

1

^CCV/r

F_{( jω)}

=

---------------------

K_PC1

=

----------

1 + jωτ₁

π

τ₁= R3 × C2;

τ₂= R4 × C2;

τ₃= R4 × C3;

A = 10⁵= DC gain

amplitude

Figure 30b

Figure 30c

Figure 30d

passive ﬁlter with

damping

1 + jωτ₂

-------------------------------------

1 + jω(τ₁+ τ₂)

active ﬁlter with

damping

1 + jωτ₂

≈

--------------------------- ---------------------

1/A + jωτ₁

jωτ₁

PC2

passive ﬁlter with

damping

5

1 + jωτ₂

K_PC

+

V/r

------

≈

---------------------------- ---------------------

4π

1 ⁄ A + jωτ₁

A = 10⁵= DC gain amplitude

1 + jωτ₂1 + jωτ₂

jωτ₁

τ₁= R3’ × C2;

τ₂= R4 × C2;

τ₃= R4 × C3;

R3' = R_bias/17;

R_bias= 25 kΩ to 250 kΩ

Figure 30e

active ﬁlter with

damping

F_{( jω)}

=

≈

--------------------------- ---------------------

1/A + jωτ₁jωτ₁

A = 10⁵= DC gain amplitude

Table 10. General design considerations

Subject

Phase comparator

Design consideration

PLL locks on harmonics at

center frequency

PC1

PC2

PC1

PC2

yes

no

Noise rejection at signal input

high

low

AC ripple content when PLL is PC1

f_r= 2f_i; large ripple content at Φ_{PC_IN}= 90°

f_r= f_i; small ripple content at Φ_{PC_IN}= 0°

locked

PC2

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

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74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

AMPLITUDE

CHARACTERISTIC

POLE ZERO

DIAGRAM

PC1

CIRCUIT

F

(jω)

R3

X

1/

τ

1

1/τ

C2

1

(a)

F

(jω)

R3

1/τ

3

2

O

X

1

C3

R4

1/ τ

2

1/ τ

τ

2

τ

2

1

C2

(b)

A

C3

R4

1/τ

2

3

C2

1/A τ

X

O

1

1/τ

2

1/A τ

R3

1

A

(c)

PC2

A

R3'

1/τ

3

2

O

X 1/ Aτ

1

R4

AR3'

1/τ

2

1/Aτ

1

C2

(d)

A

C3

R4

1/τ

3

2

C2

O

X 1/ Aτ

1

1/τ

2

1/Aτ

R3'

1

A

(e)

mbd107

Fig 30. Passive and active ﬁlters for 74HCT9046A

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

30 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd103

8

7

6

5

4

3

2

10

f

0

(Hz)

10

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

10

2

3

4

5

6

7

1

10

C1 (pF)

V_CC= 5.5 V; R1 = 3 kΩ.

V_CC= 4.5 V; R1 = 3 kΩ.

V_CC= 5.5 V; R1 = 10 kΩ.

V_CC= 4.5 V; R1 = 10 kΩ.

V_CC= 5.5 V; R1 = 150 kΩ.

V_CC= 4.5 V; R1 = 150 kΩ.

V_CC= 5.5 V; R1 = 300 kΩ.

V_CC= 4.5 V; R1 = 300 kΩ.

R2 = ∞ Ω; V_{VCO_IN}= 0.5V_CC; INH = GND; T_amb= 25 °C.

Fig 31. Typical value of VCO center frequency (f₀) as a function of C1

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

31 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mbd104

8

7

6

5

4

3

2

10

f

off

(Hz)

(1)

(2)

(3)

(4)

10

2

3

4

5

6

7

1

10

C1 (pF)

V_CC= 4.5 V to 5.5 V; R1 = 3 kΩ.

V_CC= 4.5 V to 5.5 V; R1 = 10 kΩ.

V_CC= 4.5 V to 5.5 V; R1 = 150 kΩ.

V_CC= 4.5 V to 5.5 V; R1 = 300 kΩ.

R1 = ∞ Ω; V_{VCO_IN}= 0.5V_CC; INH = GND; T_amb= 25 °C.

Fig 32. Typical value of frequency offset as a function of C1

mbd105

8

10

2f

L

(Hz)

7

6

5

4

3

2

10

V

=

CC

5.5 V

4.5 V

10

−7

−6

−5

−4

−3

−2

−1

10

1

R1C1 (s)

2 f _L

K_v

=

2π(r ⁄ s ⁄ V)

---------------------------------------

V_{VCO_IN}range

V_{VCO_IN}= 1.1 V to (V_CC− 1.1) V

Fig 33. Typical frequency lock range 2f_Las a function of the product R1 and C1

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

32 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

13.2 PLL design example

The frequency synthesizer used in the design example shown in Figure 34 has the

following parameters:

Output frequency: 2 MHz to 3 MHz

Frequency steps: 100 kHz

Settling time: 1 ms

Overshoot: < 20 %

The open loop gain is:

H(s) × G(s) = K_p× K _f× K_o× K_n

and the closed loop:

Φ_u

K_p× K _f× K_o× K_n

=

------

-------------------------------------------------------

Φ_i

1 + K_p× K _f× K_o× K_n

where:

K_p= phase comparator gain

K_f= low-pass ﬁlter transfer gain

K_o= K_v/s VCO gain

K_n= ¹⁄_ndivider ratio

The programmable counter ratio K_ncan be found as follows:

f _OUT

2 MHz

--------------------

100 kHz

N_min

=

= 20

= 30

-------------

f_step

f _OUT

3 MHz

--------------------

100 kHz

N_max

-------------

f _step

The VCO is set by the values of R1, R2 and C1; R2 = 10 kΩ (adjustable).

The values can be determined using the information in Table 8.

With f₀= 2.5 MHz and f_L= 500 kHz this gives the following values (V_CC= 5.0 V):

R1 = 30 kΩ

R2 = 30 kΩ

C1 = 100 pF

The VCO gain is:

2 f _L× 2π

1 MHz

-----------------

2.8

K_v

=

× 2π ≈ 2.24 × 10⁶r ⁄ s ⁄ V

------------------------------------------

(V_CC– 1.1) – 1.1

The gain of the phase comparator PC2 is:

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

33 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

5

K_p

=

= 0.4 V ⁄ r

-----------

4 × π

Using PC2 with the passive ﬁlter as shown in Figure 34 results in a high gain loop with the

same performance as a loop with an active ﬁlter. Hence loop ﬁlter equations as for a high

gain loop should be used. The current source output of PC2 can be simulated then with a

ﬁctive ﬁlter resistance:

R_bias

R3‘ =

-----------

17

The transfer functions of the ﬁlter is given by:

1 + sτ₂

K _f

=

----------------

sτ₂

Where:

τ₁= R3‘ × C2

τ₂= R4 × C2

The characteristic equation is: 1 + K _p× K _f× K_o× K_n

This results in:

1 + sτ₂

K

1 + K _p

^vK = 0

---------------- -----

n

sτ₁

s

or:

τ

ⁿτ₁

s²+ sK _pK_vK ²+ K K K ⁄ τ = 0

----

p

v

n

1

This can be written as:

s²+ 2ξω_ns + (ω_n)²= 0

with the natural frequency ω_ndeﬁned as:

K_p× K_v× K_n

ω_n

=

--------------------------------

τ₁

and the damping value given as: ζ = 0.5 × τ₂× ω_n

In Figure 35 the output frequency response to a step of input frequency is shown.

The overshoot and settling time percentages are now used to determine ω_n.

From Figure 35 it can be seen that the damping ratio ζ = 0.707 will produce an overshoot

of less than 20 % and settle to within 5 % at ω_nt = 5. The required settling time is 1 ms.

This results in:

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

34 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

= 5 × 10³r ⁄ s

5

--

t

5

ω_n

=

------------

0.001

Rewriting the equation for natural frequency results in:

K_p× K_v× K_n

τ₁

=

--------------------------------

(ω_n)²

The maximum overshoot occurs at N_max= 30; hence K_n= ¹⁄_30:

0.4 × 2.24 × 10⁶

τ₁

=

= 0.0012

--------------------------------------

5000²× 30

When C2 = 470 nF, it follows:

τ₁

0.0012

470 × 10^–9

R3‘ =

=

= 2550 Ω

-------------------------

------

C2

Hence the current source bias resistance

R_bias= 17 × 2550 = 43 kΩ

With ζ = 0.707 (0.5 × τ₂× ω_n) it follows:

0.707

0.5 × 5000

τ₂

=

= 0.00028

-------------------------

τ₂

0.00028

470 × 10^–9

R4 =

=

= 600 Ω

-------------------------

------

C2

For extra ripple suppression a capacitor C3 can be connected in parallel with R4, with an

extra τ₃= R4 × C3.

For stability reasons τ₃should be < 0.1τ₂, hence C3 < 0.1C2 or C3 = 39 nF.

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

35 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

K

p

K

f

K

o

100 kHz

14

PHASE

COMPARATOR

PC2

R3'

4

13

9

OSCILLATOR

"HCU04"

DIVIDE BY 10

"190"

f

VCO

12

OUT

(1)

15

3

R4

11

R2

6

7

5

C3

bias

Φ_u

R

R1

K

n

C2

1 MHz

C1

PROGRAMMABLE

DIVIDER

mbd098

"4059"

(1) R3’ = ﬁctive resistance

R_bias

R3’ =

------------

17

C1 = 100 pF

C2 = 470 nF

C3 = 39 nF

R1 = 30 kΩ

R2 = 30 kΩ

R3' = 2550 Ω

R_bias= 43 kΩ

R4 = 600 Ω

Fig 34. Frequency synthesizer

mga959

1.6

1.4

−0.6

= 0.3

0.5

0.707

1.0

ζ

−0.4

−0.2

0

∆ω (t)

e

∆Φ (t)

e

∆ω /ω

e

∆Φ /ω

e

n

1.2

= 5.0

ζ

1.0

0.8

= 2.0

ζ

0.2

0.6

0.4

0.2

0.4

0.6

0.8

0

1.0

0

1

2

3

4

5

6

7

8

ω t

n

Fig 35. Type 2, second order frequency step response

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

36 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

mga952

3.1

N = 30

proportional

to output

frequency

(MHz)

N stepped from 29 to 30

2.9

2.1

2.0

1.9

step input

N stepped from 21 to 20

0

0.5

1.0

1.5

2.0

time (ms)

2.5

Fig 36. Frequency compared to the time response

Since the output frequency is proportional to the VCO control voltage, the PLL frequency

response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO.

The average frequency response, as calculated by the Laplace method, is found

experimentally by smoothing this voltage at pin VCO_IN with a simple RC ﬁlter, whose

time constant is long compared with the phase detector sampling rate but short compared

with the PLL response time.

13.3 Further information

For an extensive description and application example please refer to “Application note”

ordering number 9397 750 00078.

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

37 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

14. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

2

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.30

0.53

0.38

1.25

0.85

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

0.76

0.068 0.021 0.049 0.014

0.051 0.015 0.033 0.009

0.77

0.73

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.03

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

95-01-14

03-02-13

SOT38-4

Fig 37. Package outline SOT38-4 (DIP16)

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

38 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 38. Package outline SOT109-1 (SO16)

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

39 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 39. Package outline SOT403-1 (TSSOP16)

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

40 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

15. Abbreviations

Table 11. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

PLL

Phase Locked Loop

VCO

Voltage Controlled Oscillator

16. Revision history

Table 12. Revision history

Document ID

74HCT9046A_6

Modiﬁcations:

Release date

20090915

Data sheet status

Change notice

Supersedes

Product data sheet

-

74HCT9046A_5

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• V_i(p-p)value changed from 15 mV to 50 mV in Section 12.

• ∆f/∆T value moved from minimum to typical column Section 12.

• Package version SOT38-1 changed to SOT38-4 in Section 4 and Figure 37.

74HCT9046A_5

74HCT9046A_4

74HCT9046A_3

20031030

20030515

19990111

Product speciﬁcation

-

74HCT9046A_4

74HCT9046A_3

-

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

41 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

42 of 43

74HCT9046A

NXP Semiconductors

PLL with band gap controlled VCO

19. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

8.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Differences with respect to the familiar

74HCT4046A . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Phase comparators. . . . . . . . . . . . . . . . . . . . . . 7

Phase Comparator 1 (PC1) . . . . . . . . . . . . . . . 7

Phase Comparator 2 (PC2) . . . . . . . . . . . . . . . 9

Loop ﬁlter component selection . . . . . . . . . . . 13

8.2

8.3

8.3.1

8.3.2

8.4

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Recommended operating conditions. . . . . . . 15

Static characteristics. . . . . . . . . . . . . . . . . . . . 15

Dynamic characteristics . . . . . . . . . . . . . . . . . 20

10

11

12

13

13.1

Application information. . . . . . . . . . . . . . . . . . 27

Filter design considerations for PC1 and

PC2 of the 74HCT9046A . . . . . . . . . . . . . . . . 29

PLL design example . . . . . . . . . . . . . . . . . . . . 33

Further information . . . . . . . . . . . . . . . . . . . . . 37

13.2

13.3

14

15

16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 41

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 42

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 42

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 September 2009

Document identifier: 74HCT9046A_6


型号：	74HCT9046AN,699
厂家：	NXP
描述：	74HCT9046A - PLL with band gap controlled VCO DIP 16-Pin 光电二极管
文件：	总43页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCT9046AN,699 [NXP]

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