74HCU_技术文档

INTEGRATED CIRCUITS

DATA SHEET

FAMILY SPECIFICATIONS

HCMOS family characteristics

March 1988

File under Integrated Circuits, IC06

Philips Semiconductors

FAMILY

SPECIFICATIONS

HCMOS family characteristics

A subset of the family, designated as XX74HCTXXXXX,

with the same features and functions as the “HC-types”,

will operate at standard TTL power supply voltage

(5 V ± 10%) and logic input levels (0.8 to 2.0 V) for use as

pin-to-pin compatible CMOS replacements to reduce

power consumption without loss of speed. These types are

also suitable for converted switching from TTL to CMOS.

GENERAL

These family specifications cover the common electrical

ratings and characteristics of the entire HCMOS

74HC/HCT/HCU family, unless otherwise specified in the

individual device data sheet.

INTRODUCTION

Another subset, the XX74HCUXXXXX, consists of

single-stage unbuffered CMOS compatible devices for

application in RC or crystal controlled oscillators and other

types of feedback circuits which operate in the linear

mode.

The 74HC/HCT/HCU high-speed Si-gate CMOS logic

family combines the low power advantages of the

HE4000B family with the high speed and drive capability of

the low power Schottky TTL (LSTTL).

The family will have the same pin-out as the 74 series and

provide the same circuit functions.

HANDLING MOS DEVICES

Inputs and outputs are protected against electrostatic

effects in a wide variety of device-handling situations.

However, to be totally safe, it is desirable to take handling

precautions into account

In these families are included several HE4000B family

circuits which do not have TTL counterparts, and some

special circuits.

The basic family of buffered devices, designated as

XX74HCXXXXX, will operate at CMOS input logic levels

for high noise immunity, negligible typical quiescent supply

and input current. It is operated from a power supply of

2 to 6 V.

(see also “HANDLING PRECAUTIONS”).

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

74HC

74HCT

SYMBOL PARAMETER

UNIT CONDITIONS

min. typ. max. min. typ. max.

V_CC

V_I

DC supply voltage

2.0 5.0 6.0

4.5

0

5.0 5.5

V_CC

V

DC input voltage range

DC output voltage range

0

V_CC

+85

V_O

0

V_CC

T_amb

t_r, t_f

operating ambient temperature range −40

−40

+85

°C

see DC and AC

CHAR. per device

+125 −40

+125 °C

input rise and fall times except for

Schmitt-trigger inputs

1000

V_CC= 2.0 V

6.0 500

400

6.0 500

ns

V

_CC= 4.5 V

V_CC= 6.0 V

Note

1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating

supply voltage is 10 V.

March 1988

2

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS FOR 74HCU

74HCU

SYMBOL

PARAMETER

UNIT CONDITIONS

min. typ. max.

2.0 5.0 6.0

V_CC

V_I

DC supply voltage

V

DC input voltage range

0

V_CC

+85

V

V_O

DC output voltage range

0

V

T_amb

operating ambient temperature range

−40

°C

see DC and AC

CHAR. per device

+125 °C

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

MIN. MAX. UNIT CONDITIONS

V_CC

±I_IK

±I_OK

±I_O

DC supply voltage

−0.5 +7

V

DC input diode current

DC output diode current

20

mA

for V_I< −0.5 or V_I> V_CC+ 0.5 V

for V_O< −0.5 or V_O> V_CC+ 0.5 V

for −0.5 V < V_O< V_CC+ 0.5 V

DC output source or sink

current

standard outputs

bus driver outputs

25

35

mA

±I_CC

±I_GND

;

DC V_CCor GND current for

types with:

standard outputs

50

70

mA

bus driver outputs

T_stg

P_tot

storage temperature range

power dissipation per package

−65 +150 °C

for temperature range: −40 to +125 °C

74HC/HCT/HCU

plastic DIL

750

500

mW above +70 °C: derate linearly with 12 mW/K

mW above +70 °C: derate linearly with 8 mW/K

plastic mini-pack (SO)

Note

1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating

supply voltage is 11 V.

March 1988

3

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HC

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

V_I

OTHER

(V)

min. typ. max. min. max. min. max.

V_IH

HIGH level input

voltage

1.5 1.2

3.15 2.4

4.2 3.2

1.5

V

2.0

4.5

6.0

2.0

4.5

6.0

3.15

4.2

3.15

4.2

V_IL

LOW level input

voltage

0.8 0.5

0.5

2.1 1.35

2.8 1.8

1.35

1.8

1.35

1.8

V_OH

HIGH level output

voltage

all outputs

1.9 2.0

1.9

4.4

5.9

3.7

5.2

2.0 V_IH

−I_O= 20 µA

−I_O= 4.0 mA

−I_O= 5.2 mA

or

V_IL

4.4 4.5

5.9 6.0

3.98 4.32

5.48 5.81

4.4

4.5

5.9

6.0

V_OH

V_OL

HIGH level output

voltage

standard outputs

3.84

5.34

V

4.5 V_IH

or

V_IL

6.0

HIGH level output

voltage

bus driver outputs

3.98 4.32

5.48 5.81

3.84

5.34

3.7

5.2

4.5 V_IH

−I_O= 6.0 mA

−I_O= 7.8 mA

or

V_IL

6.0

LOW level output

voltage

all outputs

0

0.1

0.4

2.0 V_IH

I_O= 20 µA

I_O= 4.0 mA

I_O= 5.2 mA

or

V_IL

0.1

4.5

0.1

6.0

V_OL

±I_I

LOW level output

voltage

standard outputs

0.15 0.26

0.16 0.26

0.33

V

4.5 V_IH

or

V_IL

6.0

LOW level output

voltage

bus driver outputs

0.15 0.26

0.16 0.26

0.33

0.4

V

4.5 V_IH

I_O= 6.0 mA

I_O= 7.8 mA

or

V_IL

6.0

input leakage current

0.1

1.0

µA

6.0 V_CC

or

GND

±I_OZ

3-state OFF-state

current

0.5

5.0

10.0

6.0 V_IH

V_O= V_CC

or GND

or

V_IL

I_CC

quiescent supply

current

SSI

2.0

4.0

20.0

40.0

80.0

500

40.0

µA

6.0 V_CCI_O= 0

or

flip-flops

MSI

80.0

6.0

I_O= 0

GND

8.0

160.0

1000

LSI

50.0

March 1988

4

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HCT

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

V_I

OTHER

(V)

min. typ. max. min. max. min. max.

V_IH

HIGH level input

voltage

2.0 1.6

1.2

2.0

V

µA

4.5

to

5.5

V_IL

LOW level input

voltage

0.8

4.5

to

5.5

V_OH

V_OL

±I_I

HIGH level output

voltage

all outputs

4.4 4.5

3.98 4.32

0

4.4

3.7

4.5 V_IH

−I_O= 20 µA

−I_O= 4.0 mA

−I_O= 6.0 mA

I_O= 20 µA

or

V_IL

HIGH level output

voltage

standard outputs

3.84

4.5 V_IH

or

V_IL

HIGH level output

voltage

bus driver outputs

4.5 V_IH

or

V_IL

LOW level output

voltage

all outputs

0.1

0.4

1.0

4.5 V_IH

or

V_IL

LOW level output

voltage

standard outputs

0.15 0.26

0.16 0.26

0.1

0.33

1.0

4.5 V_IH

I_O= 4.0 mA

I_O= 6.0 mA

or

V_IL

LOW level output

voltage

bus driver outputs

4.5 V_IH

or

V_IL

input leakage

current

5.5 V_CC

or

GND

±I_OZ

3-state OFF-state

current

0.5

5.0

10.0 µA

5.5 V_IH

V_O= V_CCor

GND per input

pin;

or

V_IL

other inputs at

V_CCor GND;

I_O= 0

I_CC

quiescent supply

current

SSI

2.0

4.0

20.0

40.0

80.0

500

40.0 µA

80.0

5.5 V_CC

I_O= 0

or

GND

flip-flops

MSI

5.5

8.0

160.0

5.5

LSI

50.0

1000

5.5

March 1988

5

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

V_I

OTHER

(V)

min. typ. max. min. max. min. max.

100 360 450 490

∆I_CC

additional quiescent

supply current per

input pin for unit load

coefﬁcient is 1

µA

4.5 V_CC

other inputs at

to

−2.1 V V_CCor GND;

_O= 0

5.5

I

(note 1)

Note

1. The additional quiescent supply current per input is determined by the ∆I_CCunit load, which has to be multiplied by

the unit load coefficient as given in the individual data sheets. For dual supply systems the theoretical worst-case

(V_I= 2.4 V; V_CC= 5.5 V) specification is: ∆I_CC= 0.65 mA (typical) and 1.8 mA (maximum) across temperature.

March 1988

6

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HCU

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HCU

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

V_I

OTHER

(V)

min. typ. max. min. max. min. max.

V_IH

HIGH level input

voltage

1.7 1.4

3.6 2.6

4.8 3.4

1.7

3.6

4.8

1.7

3.6

4.8

V

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

V_IL

LOW level input

voltage

0.6 0.3

0.3

0.9

1.2

0.3

0.9

1.2

1.9 0.9

2.6 1.2

V_OH

HIGH level output

voltage

1.8 2.0

1.8

4.0

5.5

3.7

5.2

V_IH

or

V_IL

−I_O= 20 µA

−I_O= 4.0 mA

−I_O= 5.2 mA

4.0 4.5

5.5 6.0

3.98 4.32

5.48 5.81

4.0

5.5

V_OH

HIGH level output

voltage

3.84

5.34

V

V_CC

or

GND

V_OL

LOW level output

voltage

0

0.2

0.5

0.2

0.5

0.4

2.0

4.5

6.0

4.5

6.0

V_IH

or

V_IL

I_O= 20 µA

I_O= 4.0 mA

I_O= 5.2 mA

0.5

V_OL

LOW level output

voltage

0.15 0.26

0.16 0.26

0.33

V

V_CC

or

GND

±I_I

input leakage current

0.1

1.0

µA

6.0

V_CC

or

GND

I_CC

quiescent supply

current SSI

2.0

20.0

40.0 µA

6.0

V_CC

or

I_O= 0

GND

March 1988

7

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

ns

WAVEFORMS

Figs 3 and 4

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_THL/ t_TLHoutput transition time

standard outputs

19

7

75

15

13

60

12

10

95

19

16

75

15

13

110

22

19

90

18

15

2.0

4.5

6.0

2.0

4.5

6.0

6

t

_THL/ t_TLHoutput transition time

bus driver outputs

14

5

ns

4

AC CHARACTERISTICS FOR 74HCU

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T

_amb(°C)

74HCU

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

TEST CONDITIONS

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

t_THL/ t_TLHoutput transition time

19

7

75

15

13

95

19

16

110

22

ns

2.0

4.5

6.0

Fig.1

6

19

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T

_amb(°C)

74HCT

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

TEST CONDITIONS

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

t_THL/ t_TLHoutput transition time

standard outputs

7

5

15

12

19

15

22

18

ns

4.5

Figs 8 and 9

t_THL/ t_TLHoutput transition time

bus driver outputs

March 1988

8

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

HCU TYPES

AC waveforms 74HCU

t

f

handbook, halfpage

r

V

CC

90%

50%

INPUT

10%

GND

t

PHL

90%

PLH

50%

10%

OUTPUT

t

THL

TLH

MGK564

Fig.1 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

Test circuit for 74HCU

V

handbook, halfpage

CC

V

I

O

PULSE

GENERATOR

D.U.T

R

C

50 pF

T

L

MGK565

C_L

R_T

=

load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

termination resistance should be equal to the output impedance Z_oof

the pulse generator.

Fig.2 Test circuit.

March 1988

9

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

HC TYPES

AC waveforms 74HC

t

f

handbook, halfpage

r

V

CC

90%

50%

INPUT

10%

GND

t

PHL

90%

PLH

50%

10%

OUTPUT

t

THL

TLH

MGK564

Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

AC waveforms 74HC

1/f

handbook, full pagewidth

max

t

r

f

V

CC

90%

50%

CLOCK

INPUT

10 %

GND

t

WL

WH

t

h

V

CC

DATA

INPUT

50%

GND

t

su

t

THL

TLH

90%

50%

OUTPUT

10%

t

PHL

PLH

t

rem

V

CC

SET,

RESET,

PRESET

INPUT

50%

GND

MGK569

(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET

and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals

are specified in the individual device data sheet.

(2) For AC measurements: t_r= t_f= 6 ns; when measuring f_max, there is no constraint on t_r, t_fwith 50% duty factor.

Fig.4 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for

sequential logic ICs.

March 1988

10

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

Test circuit for 74HC

V

handbook, halfpage

CC

V

I

O

PULSE

GENERATOR

D.U.T

R

C

50 pF

T

L

MGK565

C_L

R_T

=

load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

termination resistance should be equal to the output impedance Z_oof

the pulse generator.

Fig.5 Test circuit.

AC waveforms 74HC (continued)

t

r

handbook, full pagewidth

f

V

CC

90%

50%

OUTPUT

ENABLE

10%

t

GND

t

PLZ

PZL

OUTPUT

LOW-to-OFF

OFF-to-LOW

50%

10%

t

PHZ

PZH

90%

OUTPUT

50%

HIGH-to-OFF

OFF-to-HIGH

outputs

enabled

outputs

enabled

outputs

disabled

MGK562

Fig.6 Propagation delays of 3-state outputs.

March 1988

11

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

Test circuit for 74HC

V

handbook, full pagewidth

CC

V

R

= 1 kΩ

I

O

L

PULSE

GENERATOR

D.U.T

R

C

50 pF

T

L

MGK563

Switch position

TEST

SWITCH

t_PZH

t_PZL

t_PHZ

t_PLZ

GND

V_CC

GND

V_CC

Note

1. For open-drain N-channel outputs t_PLZand t_PZLare applicable.

C_L

R_T

=

load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

termination resistance should be equal to the output impedance Z_oof

the pulse generator.

Fig.7 Test circuit for 3-state outputs.

HCT TYPES

AC waveforms 74HCT

t

f

handbook, halfpage

INPUT

r

3 V

90%

1.3 V

10%

GND

t

PHL

90%

PLH

1.3 V

10%

OUTPUT

t

THL

TLH

MGK567

Fig.8 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

March 1988

12

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC waveforms 74HCT

1/f

handbook, full pagewidth

max

t

r

f

3 V

90%

CLOCK

INPUT

1.3 V

10%

GND

t

WH

WL

t

h

3 V

DATA

INPUT

1.3 V

GND

t

su

t

TLH

THL

90%

1.3 V

OUTPUT

10%

t

PHL

PLH

t

rem

3 V

SET,

RESET,

PRESET

INPUT

1.3 V

GND

MGK568

(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals

(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual

active levels of the forcing signals are specified in the individual device data sheet.

(2) For AC measurements: t_r= t_f= 6 ns; when measuring f_max, there is no constraint on t_r, t_fwith 50% duty factor.

Fig.9 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for

sequential logic ICs.

Test circuit for 74HCT

V

handbook, halfpage

CC

V

I

O

PULSE

GENERATOR

D.U.T

R

C

50 pF

T

L

MGK565

C_L

R_T

=

load capacitance including jig and probe capacitance (see AC

CHARACTERISTICS for values).

termination resistance should be equal to the output impedance Z_oof

the pulse generator.

Fig.10 Test circuit.

13

March 1988

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC waveforms 74HCT (continued)

t

r

handbook, full pagewidth

f

90%

OUTPUT

ENABLE

1.3 V

10%

t

PLZ

PZL

OUTPUT

LOW-to-OFF

OFF-to-LOW

1.3 V

10%

t

PHZ

PZH

90%

OUTPUT

1.3 V

HIGH-to-OFF

OFF-to-HIGH

outputs

enabled

outputs

enabled

outputs

disabled

MGK566

Fig.11 Propagation delays of 3-state outputs.

Test circuit for 74HCT

V

handbook, full pagewidth

CC

V

R

= 1 kΩ

I

O

L

PULSE

GENERATOR

D.U.T

R

C

50 pF

T

L

MGK563

Switch position

TEST

SWITCH

t_PZH

t_PZL

t_PHZ

t_PLZ

GND

V_CC

GND

V_CC

Note

1. For open-drain N-channel outputs t_PLZand t_PZLare applicable.

C_L

R_T

=

load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

termination resistance should be equal to the output impedance Z_oof

the pulse generator.

Fig.12 Test circuit for 3-state outputs.

March 1988

14

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

conditions under which the limits in the “DC

DATA SHEET SPECIFICATION GUIDE

INTRODUCTION

CHARACTERISTICS” and “AC CHARACTERISTICS”

tables will be met. The table should not be seen as a set of

limits guaranteed by the manufacturer, but as the

conditions used to test the devices and guarantee that

they will then meet the limits in the DC and AC

CHARACTERISTICS tables.

The 74HCMOS data sheets have been designed for

ease-of-use. A minimum of cross-referencing for more

information is needed.

TYPICAL PROPAGATION DELAY AND FREQUENCY

DC CHARACTERISTICS

The typical propagation delays listed at the top of the data

sheets are the average of t_PLHand t_PHLfor the longest data

path through the device with a 15 pF load.

The “DC CHARACTERISTICS” table reflects the DC limits

used during testing. The values published are guaranteed.

The threshold values of V_IHand V_ILcan be tested by the

user. If V_IHand V_ILare applied to the inputs, the output

voltages will be those published in the “DC

CHARACTERISTICS” table. There is a tendency, by

some, to use the published V_IHand V_ILthresholds to test a

device for functionality in a “function-table exercizer”

mode. This frequently causes problems because of the

noise present at the test head of automated test

For clocked devices, the maximum frequency of operation

is also given. The typical operating frequency is the

maximum device operating frequency with a 50% duty

factor and no constraints on t_rand t_f.

LOGIC SYMBOLS

Two logic symbols are given for each device - the

conventional one (Logic Symbol) which explicitly shows

the internal logic (except for complex logic) and the IEC

Logic Symbol as developed by the IEC (International

Electrotechnical Commission).

equipment with cables up to 1 metre. Parametric tests,

such as those used for the output levels under the V_IHand

V_ILconditions are done fairly slowly, in the order of

milliseconds, so that there is no noise at the inputs when

the outputs are measured. But in functionality testing, the

outputs are measured much faster, so there can be noise

on the inputs, before the device has assumed its final and

correct output state. Thus, never use V_IHand V_ILto test the

functionality of any HCMOS device type; instead, use input

voltages of V_CC(for the HIGH state) and 0 V (for the LOW

state). In no way does this imply that the devices are

noise-sensitive in the final system.

The IEC has been developing a very powerful symbolic

language that can show the relationship of each input of a

digital logic current to each output without explicitly

showing the internal logic.

Internationally, Working Group 2 of IEC Technical

Committee TC-3 has prepared a new document

(Publication 617-12) which supersedes

Publication 117-15, published in 1972.

In the data sheets, it may appear strange that the typical

V_ILis higher than the maximum V_IL. However, this is

because V_ILmaxis the maximum V_IL(guaranteed) for all

devices that will be recognized as a logic LOW. However,

typically a higher V_ILwill also be recognized as a logic

LOW. Conversely, the typical V_IHis lower than its minimum

guaranteed level.

RATINGS

The “RATINGS” table (Limiting values in accordance with

the Absolute Maximum System - IEC134) lists the

maximum limits to which the device can be subjected

without damage. This doesn’t imply that the device will

function at these extreme conditions, only that, when these

conditions are removed and the device operated within the

Recommended Operating Conditions, it will still be

functional and its useful life won’t have been shortened.

For 74HCMOS, unlike TTL, no output HIGH short-circuit

current is specified. The use of this current, for example, to

calculate propagation delays with capacitive loads, is

covered by the HCMOS graphs showing the output drive

capability and those showing the dependence of

propagation delay on load capacitance.

The maximum rated supply voltage of 7 V is well below the

typical breakdown voltage of 18 V.

The quiescent supply current I_CCis the leakage current of

all the reversed-biased diodes and the OFF-state MOS

transistors. It is measured with the inputs at V_CCor GND

and is typically a few nA.

RECOMMENDED OPERATING CONDITIONS

The “RECOMMENDED OPERATING CONDITIONS”

table lists the operating ambient temperature and the

March 1988

15

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC CHARACTERISTICS

The “AC CHARACTERISTICS” table lists the guaranteed

limits when a device is tested under the conditions given in

the AC Test Circuits and Waveforms section.

TEST CIRCUITS

Good high-frequency wiring practices should be used in

test circuits. Capacitor leads should be as short as

possible to minimize ripples on the output waveform

transitions and undershoot. Generous ground metal

(preferably a ground-plane) should be used for the same

reasons. A V_CCdecoupling capacitor should be provided

at the test socket, also with short leads. Input signals

should have rise and fall times of 6 ns, a signal swing of

0 V to V_CCfor 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz

square wave is recommended for most propagation delay

tests. The repetition rate must be increased for testing

f_max. Two pulse generators are usually required for testing

such parameters as set-up time, hold time and removal

time. f_maxis also tested with 6 ns input rise and fall times,

with a 50% duty factor, but for typical f_maxas high as

60 MHz, there are no constraints on rise and fall times.

March 1988

16

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

DEFINITIONS OF SYMBOLS AND TERMS USED IN

HCMOS DATA SHEETS

Currents

V_IL

LOW level input voltage; the range of input

voltages that represents a logic LOW level in

the system.

Positive current is deﬁned as conventional current ﬂow

into a device.

Negative current is deﬁned as conventional current ﬂow

out of a device.

V_OH

HIGH level output voltage; the range of

voltages at an output terminal with a speciﬁed

output loading and supply voltage. Device

inputs are conditioned to establish a HIGH level

at the output.

I_CC

∆I_CC

I_GND

I_I

Quiescent power supply current; the current

ﬂowing into the V_CCsupply terminal.

Additional quiescent supply current per input

pin at a speciﬁed input voltage and V_CC

.

V_OL

LOW level output voltage; the range of voltages

at an output terminal with a speciﬁed output

loading and supply voltage. Device inputs are

conditioned to establish a LOW level at the

output.

Quiescent power supply current; the current

ﬂowing into the GND terminal.

Input leakage current; the current ﬂowing into a

device at a speciﬁed input voltage and V_CC

.

I_IK

Input diode current; the current ﬂowing into a

device at a speciﬁed input voltage.

V_T+

Trigger threshold voltage; positive-going signal.

V_T−

Trigger threshold voltage; negative-going

signal.

I_O

Output source or sink current: the current

ﬂowing into a device at a speciﬁed output

voltage.

Analog terms

R_ONON-resistance; the effective ON-state

I_OK

I_OZ

Output diode current; the current ﬂowing into a

device at a speciﬁed output voltage.

resistance of an analog switch, at a speciﬁed

voltage across the switch and output load.

OFF-state output current; the leakage current

ﬂowing into the output of a 3-state device in the

OFF-state, when the output is connected to

∆R_ON∆ON-resistance; the difference in

ON-resistance between any two switches of an

analog device at a speciﬁed voltage across the

switch and output load.

V

_CCor GND.

I_S

Analog switch leakage current; the current

ﬂowing into an analog switch at a speciﬁed

voltage across the switch and V_CC

.

Capacitances

C_I

Input capacitance; the capacitance measured

at a terminal connected to an input of a device.

Voltages

All voltages are referenced to GND (ground), which is

typically 0 V.

C_I/O

Input/Output capacitance; the capacitance

measured at a terminal connected to an I/O-pin

(e.g. a transceiver).

GND

Supply voltage; for a device with a single

negative power supply, the most negative

power supply, used as the reference level for

other voltages; typically ground.

C_L

Output load capacitance; the capacitance

connected to an output terminal including jig

and probe capacitance.

C_PD

Power dissipation capacitance; the capacitance

used to determine the dynamic power

dissipation per logic function, when no extra

load is provided to the device.

V_CC

V_EE

V_H

Supply voltage; the most positive potential on

the device.

Supply voltage; one of two (GND and V_EE

)

negative power supplies.

C_S

Switch capacitance; the capacitance of a

terminal to a switch of an analog device.

Hysteresis voltage; difference between the

trigger levels, when applying a positive and a

negative-going input signal.

V_IH

HIGH level input voltage; the range of input

voltages that represents a logic HIGH level in

the system.

March 1988

17

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC switching parameters

t_PLZ

t_PZH

t_PZL

3-state output disable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and the 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and a point

representing 10% of the output swing on the

output voltage waveform of a 3-state

f_i

Input frequency; for combinatorial logic devices

the maximum number of inputs and outputs

switching in accordance with the device

function table. For sequential logic devices the

clock frequency using alternate HIGH and LOW

for data input or using the toggle mode,

whichever is applicable.

device, with the output changing from a LOW

level (V_OL) to a high impedance OFF-state (Z).

f_o

Output frequency; each output.

f_max

Maximum clock frequency; clock input

waveforms should have a 50% duty factor and

be such as to cause the outputs to be switching

from 10%V_CCto 90%V_CCin accordance with

the device function table.

3-state output enable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and the 50%

point on the output voltage waveform of a

3-state device, with the output changing from a

high impedance OFF-state (Z) to a HIGH level

(V_OH).

t_h

Hold time; the interval immediately following the

active transition of the timing pulse (usually the

clock pulse) or following the transition of the

control input to its latching level, during which

interval the data to be recognized must be

maintained at the input to ensure their

continued recognition. A negative hold time

indicates that the correct logic level may be

released prior to the timing pulse and still be

recognized.

3-state output enable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and the 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and the 50%

point on the output voltage waveform of a

3-state device, with the output changing from a

high impedance OFF-state (Z) to a LOW level

(V_OL).

t_r,

t_f

Clock input rise and fall times; 10% and 90%

values.

t_PHL

t_PLH

t_PHZ

Propagation delay; the time between the

speciﬁed reference points, normally the 50%

points for 74HC and 74HCU devices on the

input and output waveforms and the 1.3 V

points for the 74HCT devices, with the output

changing from the deﬁned HIGH level to the

deﬁned LOW level.

t_rem

Removal time; the time between the end of an

overriding asynchronous input, typically a clear

or reset input, and the earliest permissible

beginning of a synchronous control input,

typically a clock input, normally measured at

the 50% points for 74HC devices and the 1.3 V

points for the 74HCT devices on both input

voltage waveforms.

Propagation delay; the time between the

speciﬁed reference points, normally the 50%

points for 74HC and 74HCU devices on the

input and output waveforms and the 1.3 V point

for the 74HCT devices, with the output

changing from the deﬁned LOW level to the

deﬁned HIGH level.

t_su

Set-up time; the interval immediately preceding

the active transition of the timing pulse (usually

the clock pulse) or preceding the transition of

the control input to its latching level, during

which interval the data to be recognized must

be maintained at the input to ensure their

recognition. A negative set-up time indicates

that the correct logic level may be initiated

sometime after the active transition of the

timing pulse and still be recognized.

3-state output disable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC and 74HCU devices

and the 1.3 V points for the 74HCT devices on

the output enable input voltage waveform and a

point representing 10% of the output swing on

the output voltage waveform of a 3-state

device, with the output changing from

a HIGH level (V_OH) to a high impedance

OFF-state (Z).

March 1988

18

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

t_THL

t_W

Output transition time; the time between two

speciﬁed reference points on a waveform,

normally 90% and 10% points, that is changing

from HIGH-to-LOW.

Output transition time; the time between two

speciﬁed reference points on a waveform,

normally 10% and 90% points, that is changing

from LOW-to-HIGH.

Pulse width; the time between the 50%

amplitude points on the leading and trailing

edges of a pulse for 74HC and 74HCU devices

and at the 1.3 V points for 74HCT devices.

March 1988

19


型号：	74HCU
厂家：	NXP
描述：	HCMOS family characteristics HCMOS系列特点
文件：	总19页 (文件大小：90K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCU [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB