74LV00D,118 [NXP]
74LV00 - Quad 2-input NAND gate SOIC 14-Pin;
| 型号： | 74LV00D,118 |
| 厂家： | 
NXP |
| 描述： | 74LV00 - Quad 2-input NAND gate SOIC 14-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV00
Quad 2-input NAND gate
Rev. 03 — 20 December 2007
Product data sheet
1. General description
The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC00 and 74HCT00.
The 74LV00 provides a quad 2-input NAND function.
2. Features
■ Wide operating voltage: 1.0 V to 5.5 V
■ Optimized for low voltage applications: 1.0 V to 3.6 V
■ Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
■ Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
■ Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV00N
74LV00D
−40 °C to +125 °C
−40 °C to +125 °C
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
SOT108-1
plastic small outline package; 14 leads;
body width 3.9 mm
74LV00DB
74LV00PW
74LV00BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
SOT402-1
SOT762-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74LV00
NXP Semiconductors
Quad 2-input NAND gate
4. Functional diagram
1
2
3
&
&
&
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
mna211
mna212
mna246
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74LV00
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
1Y
2A
2B
2Y
4B
4A
4Y
3B
3A
3Y
1Y
2A
00
(1)
CC
V
2B
2Y
8
GND
001aah092
001aac938
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input
data input
data output
data input
data input
data output
1B
2
1Y
3
2A
4
2B
5
2Y
6
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
2 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
Table 2.
Symbol
GND
3Y
Pin description …continued
Pin
7
Description
ground (0 V)
data output
data input
8
3A
9
3B
10
11
12
13
14
data input
4Y
data output
data input
4A
4B
data input
VCC
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
X
nY
H
X
L
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±50
±25
50
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
+150
Tamb = −40 °C to +125 °C
DIP14 package
[2]
[3]
[4]
[5]
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 °C.
[3] Ptot derates linearly with 8 mW/K above 70 °C.
[4] Ptot derates linearly with 5.5 mW/K above 60 °C.
[5] Ptot derates linearly with 4.5 mW/K above 60 °C.
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
3 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
[1]
VCC
VI
supply voltage
1.0
3.3
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level input voltage
HIGH-level output voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOH
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
IO = −100 µA; VCC = 4.5 V
IO = −6 mA; VCC = 3.0 V
IO = −12 mA; VCC = 4.5 V
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
4 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
IO = 100 µA; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
V
0
0.2
0.2
0.2
0.2
0.2
0.50
0.65
1.0
40
V
0
0.2
V
0
0.2
V
0
0.25
0.35
-
0.2
V
0.40
0.55
1.0
V
V
II
input leakage current
supply current
µA
µA
ICC
-
20.0
V
CC = 5.5 V
per input; VI = VCC − 0.6 V;
CC = 2.7 V to 3.6 V
∆ICC
additional supply current
input capacitance
-
-
-
500
-
-
-
850
-
µA
V
CI
3.5
pF
[1] Typical values are measured at Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1] Max
Min
Max
[2]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 1.2 V
-
-
-
-
-
-
-
45
15
11
7
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
26
18
-
31
23
-
VCC = 2.7 V
[3]
[3]
[3]
[4]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
9.0
6.5
22
15
11
-
18
14
-
VCC = 4.5 V to 5.5 V
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance
VI = GND to VCC
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
5 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
11. Waveforms
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
V
nY output
M
V
OL
001aah088
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
2.7 V to 3.6 V
≥ 4.5 V
0.5VCC
V
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
R
L
1 kΩ
L
R
T
001aaa663
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
Table 9.
Test data
Supply voltage
VCC
Input
VI
tr, tf
< 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V to 3.6 V
≥ 4.5 V
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
6 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 8. Package outline SOT27-1 (DIP14)
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
7 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 9. Package outline SOT108-1 (SO14)
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
8 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 10. Package outline SOT337-1 (SSOP14)
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
9 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
10 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 12. Package outline SOT762-1 (DHVQFN14)
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
11 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LV00_3
Release date
20071220
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV00_2
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN14 package added.
• Section 7: derating values added for DHVQFN14 package.
• Section 12: outline drawing added for DHVQFN14 package.
74LV00_2
74LV00_1
19980420
Product specification
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74LV00_1
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19970203
Product specification
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74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
12 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LV00_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 20 December 2007
13 of 14
74LV00
NXP Semiconductors
Quad 2-input NAND gate
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 December 2007
Document identifier: 74LV00_3
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