74LV132PW,118 [NXP]
74LV132 - Quad 2-input NAND Schmitt trigger TSSOP 14-Pin;型号: | 74LV132PW,118 |
厂家: | NXP |
描述: | 74LV132 - Quad 2-input NAND Schmitt trigger TSSOP 14-Pin 光电二极管 逻辑集成电路 |
文件: | 总17页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV132
Quad 2-input NAND Schmitt trigger
Rev. 6 — 9 December 2015
Product data sheet
1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals.
They are capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage VT is defined as the
input hysteresis voltage VH.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV132D
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT337-1
SOT402-1
SOT762-1
74LV132DB
74LV132PW
74LV132BQ
SSOP14
TSSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
5. Functional diagram
ꢀ$
ꢀ
ꢀ<
ꢁ
ꢀ%
ꢂ
ꢂ$
ꢃ
ꢀ
ꢂ<
ꢄ
ꢉ
ꢁ
ꢂ%
ꢅ
ꢂ
ꢃ
ꢉ
ꢉ
ꢉ
ꢁ$
ꢆ
ꢄ
ꢇ
ꢅ
ꢁ<
ꢇ
ꢁ%
ꢀꢈ
ꢆ
ꢀꢈ
ꢃ$
ꢀꢂ
$
%
ꢀꢂ
ꢀꢁ
ꢃ<
ꢀꢀ
ꢀꢀ
<
ꢃ%
ꢀꢁ
PQDꢀꢁꢂ
PQDꢀꢁꢃ
PQDꢀꢁꢄ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
2 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
74LV132
terminal 1
index area
ꢀ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
ꢊ
ꢀꢃ
ꢀꢁ
ꢀꢂ
ꢀꢀ
ꢀꢈ
ꢆ
ꢀ$
ꢀ%
9
&&
ꢃ%
ꢃ$
ꢃ<
ꢁ%
ꢁ$
ꢁ<
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1Y
2A
2B
2Y
ꢀ<
ꢂ$
ꢀꢁꢂ
(1)
CC
V
ꢂ%
ꢂ<
001aah099
ꢇ
*1'
Transparent top view
ꢁꢁꢅDDFꢆꢁꢇ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC
.
Fig 4. Pin configuration SO14 and (T)SSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
Pin description
Pin
Description
data input
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
7. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
nA
L
nB
L
nY
H
L
H
L
H
H
H
H
H
L
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
3 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max Unit
supply voltage
0.5
+7.0
20
50
25
50
V
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
IOK
-
-
IO
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150 C
Tamb = 40 C to +125 C
SO14 package
[2]
[3]
[4]
-
-
-
500
500
500
mW
(T)SSOP14 package
DHVQFN14 package
mW
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] tot derates linearly with 8 mW/K above 70 C.
P
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
supply voltage[1]
Conditions
Min
1.0
0
Typ
3.3
-
Max
5.5
Unit
V
input voltage
VCC
VCC
+125
V
VO
output voltage
ambient temperature
0
-
V
Tamb
40
+25
C
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
4 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOH
HIGH-level output voltage VI = VT+ or VT
lO = 100 A; VCC = 1.2 V
lO = 100 A; VCC = 2.0 V
lO = 100 A; VCC = 2.7 V
lO = 100 A; VCC = 3.0 V
lO = 100 A; VCC = 4.5 V
lO = 6 mA; VCC = 3.0 V
lO = 12 mA; VCC = 4.5 V
VI = VT+ or VT
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
VOL
LOW-level output voltage
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.25
0.35
-
V
V
II
input leakage current
supply current
VI = VCC or GND;
VCC = 5.5 V
A
ICC
ICC
CI
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
-
20.0
500
-
-
-
-
40
850
-
A
A
pF
additional supply current
input capacitance
per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V
3.5
[1] Typical values are measured at Tamb = 25 C.
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
5 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions
40 C to +85 C
Min
Typ[1] Max
40 C to +125 C
Unit
Min
Max
[2]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 1.2 V
-
-
-
-
-
-
-
65
18
15
10
12
9.0
24
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
34
24
-
43
30
-
VCC = 2.7 V
[3]
[3]
[3]
[4]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
20
14
-
25
17
-
VCC = 4.5 V to 5.5 V
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance
VI = GND to VCC
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
9
,
9
Q$ꢋꢌQ%ꢌLQSXW
0
*1'
W
W
3+/
3/+
9
2+
9
Q<ꢌRXWSXW
0
9
2/
ꢁꢁꢅDDDꢈꢈꢆ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
6 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
2.7 V to 3.6 V
4.5 V
0.5VCC
9
&&
9
9
2
,
38/6(ꢌ
*(1(5$725
'87ꢌ
&
/ꢌ
ꢅꢈꢌS)
5
/ꢌ
ꢀꢌNȍ
5
7
ꢁꢁꢅDDDꢈꢈꢇ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
VCC
Input
VI
tr, tf
< 2.7 V
VCC
2.7 V
VCC
2.5 ns
2.5 ns
2.5 ns
2.7 V to 3.6 V
4.5 V
13. Transfer characteristics
Table 10. Transfer characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1] Max
Min
Max
VT+
positive-going
threshold voltage
see Figure 6
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
-
0.70
1.10
1.45
1.60
1.95
2.50
3.00
-
-
-
V
V
V
V
V
V
V
0.8
1.0
1.2
1.5
1.7
2.1
1.4
2.0
2.2
2.4
3.2
3.9
0.8
1.0
1.2
1.5
1.7
2.1
1.4
2.0
2.2
2.4
3.2
3.9
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
7 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Table 10. Transfer characteristics …continued
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
Conditions
40 C to +85 C
Min
Typ[1] Max
40 C to +125 C
Unit
Min
Max
VT
negative-going
threshold voltage
see Figure 6
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
-
0.34
0.65
0.90
1.05
1.30
1.60
2.00
-
-
-
V
V
V
V
V
V
V
0.3
0.4
0.6
0.8
0.9
1.2
0.9
1.4
1.5
1.8
2.0
2.6
0.3
0.4
0.6
0.8
0.9
1.2
0.9
1.4
1.5
1.8
2.0
2.6
VH
hysteresis voltage (VT+ VT); see Figure 6
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
-
0.3
-
-
-
V
V
V
V
V
V
V
0.2
0.3
0.4
0.4
0.4
0.6
0.55
0.60
0.65
0.70
0.80
1.00
0.8
1.1
1.2
1.2
1.4
1.5
0.2
0.3
0.4
0.4
0.4
0.6
0.8
1.1
1.2
1.2
1.4
1.5
[1] All typical values are measured at Tamb = 25 C.
14. Waveforms transfer characteristics
9
2
9
7ꢍ
9
,
9
+
9
7ꢎ
9
,
9
9
2
+
9
9
7ꢍ
7ꢎ
PQDꢆꢁꢂ
PQDꢆꢁꢃ
VT+ and VT limits at 70 % and 20 %.
Fig 8. Transfer characteristic
Fig 9. Definition of VT+, VT and VH
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
8 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
ꢁꢁꢅDDDꢈꢉꢄ
ꢁꢁꢅDDDꢈꢈꢁ
ꢀꢂ
ꢀꢈꢈ
,
&&ꢌ
ꢏ$ꢐ
,
&&ꢌ
ꢏ$ꢐ
ꢇꢈ
ꢇ
ꢃ
ꢈ
ꢄꢈ
ꢃꢈ
ꢂꢈ
ꢈ
ꢈ
ꢈꢑꢁ
ꢈꢑꢄ
ꢈꢑꢆ
ꢀꢑꢂ
ꢈ
ꢈꢑꢃ
ꢈꢑꢇ
ꢀꢑꢂ
ꢀꢑꢄ
ꢂ
9 ꢌꢏ9ꢐ
,
9 ꢏ9ꢐ
,ꢌ
VCC = 1.2 V.
VCC = 2.0 V.
Fig 10. Typical 74LV132 transfer characteristics
Fig 11. Typical 74LV132 transfer characteristics
ꢁꢁꢅDDDꢈꢈꢅ
ꢁꢈꢈ
,
ꢌ
&&
ꢏ$ꢐ
ꢂꢈꢈ
ꢀꢈꢈ
ꢈ
ꢈ
ꢈꢑꢄ
ꢀꢑꢂ
ꢀꢑꢇ
ꢂꢑꢃ
ꢁ
9 ꢏ9ꢐ
,ꢌ
VCC = 3.0 V.
Fig 12. Typical 74LV132 transfer characteristics
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
9 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
15. Package outline
62ꢀꢇꢈꢃSODVWLFꢃVPDOOꢃRXWOLQHꢃSDFNDJHꢉꢃꢀꢇꢃOHDGVꢉꢃERG\ꢃZLGWKꢃꢁꢄꢊꢃPPꢃ
627ꢀꢋꢌꢍꢀꢃ
'ꢌ
(ꢌ
$ꢌ
;ꢌ
Fꢌ
\ꢌ
+ꢌ
(ꢌ
Yꢌ 0ꢌ
$ꢌ
=ꢌ
ꢇꢌ
ꢀꢃꢌ
4ꢌ
$ꢌ
ꢂꢌ
$ꢌ
ꢏ$ꢌꢌꢐꢌ
ꢁꢌ
$ꢌ
ꢀꢌ
SLQꢌꢀꢌLQGH[ꢌ
șꢌ
/ꢌ
Sꢌ
/ꢌ
ꢀꢌ
ꢊꢌ
Hꢌ
GHWDLOꢌ;ꢌ
Zꢌ 0ꢌ
Eꢌ
Sꢌ
ꢈꢌ
ꢂꢑꢅꢌ
VFDOHꢌ
ꢅꢌPPꢌ
',0(16,216ꢃꢅLQFKꢃGLPHQVLRQVꢃDUHꢃGHULYHGꢃIURPꢃWKHꢃRULJLQDOꢃPPꢃGLPHQVLRQVꢆꢃ
$ꢃ
ꢅꢀꢆꢃ
ꢅꢀꢆꢃ
ꢅꢀꢆꢃ
81,7ꢃ
$ꢃ
ꢀꢃ
$ꢃ
ꢂꢃ
$ꢃ
ꢁꢃ
Eꢃ
Sꢃ
Fꢃ
'ꢃ
(ꢃ
Hꢃ
+ꢃ
(ꢃ
/ꢃ
/ꢃ
Sꢃ
4ꢃ
Yꢃ
Zꢃ
\ꢃ
=ꢃ
șꢌ
PD[ꢄꢃ
ꢈꢑꢂꢅꢌ ꢀꢑꢃꢅꢌ
ꢈꢑꢀꢈꢌ ꢀꢑꢂꢅꢌ
ꢈꢑꢃꢆꢌ ꢈꢑꢂꢅꢌ ꢇꢑꢊꢅꢌ
ꢈꢑꢁꢄꢌ ꢈꢑꢀꢆꢌ ꢇꢑꢅꢅꢌ
ꢃꢑꢈꢌ
ꢁꢑꢇꢌ
ꢄꢑꢂꢌ
ꢅꢑꢇꢌ
ꢌ
ꢀꢑꢈꢌ
ꢈꢑꢃꢌ
ꢈꢑꢊꢌ
ꢈꢑꢄꢌ
ꢈꢑꢊꢌ
ꢈꢑꢁꢌ
PPꢌ
ꢀꢑꢊꢅꢌ
ꢀꢑꢂꢊꢌ
ꢈꢑꢈꢅꢌ
ꢀꢑꢈꢅꢌ
ꢈꢑꢂꢅꢌ ꢈꢑꢂꢅꢌ
ꢈꢑꢀꢌ
ꢈꢑꢂꢅꢌ
ꢈꢑꢈꢀꢌ
Rꢌ
ꢇꢌ
Rꢌ
ꢈꢌ
ꢈꢑꢈꢀꢈꢌ ꢈꢑꢈꢅꢊꢌ
ꢈꢑꢈꢈꢃꢌ ꢈꢑꢈꢃꢆꢌ
ꢈꢑꢈꢀꢆꢌ ꢈꢑꢈꢀꢈꢈꢌ ꢈꢑꢁꢅꢌ ꢈꢑꢀꢄꢌ
ꢈꢑꢈꢀꢃꢌ ꢈꢑꢈꢈꢊꢅꢌ ꢈꢑꢁꢃꢌ ꢈꢑꢀꢅꢌ
ꢈꢑꢂꢃꢃꢌ
ꢈꢑꢂꢂꢇꢌ
ꢈꢑꢈꢁꢆꢌ ꢈꢑꢈꢂꢇꢌ
ꢈꢑꢈꢀꢄꢌ ꢈꢑꢈꢂꢃꢌ
ꢈꢑꢈꢂꢇꢌ
ꢈꢑꢈꢀꢂꢌ
LQFKHVꢌ
ꢈꢑꢈꢃꢀꢌ
ꢈꢑꢈꢀꢌ ꢈꢑꢈꢀꢌ ꢈꢑꢈꢈꢃꢌ
ꢈꢑꢈꢄꢆꢌ
1RWHꢃ
ꢀꢑꢌ3ODVWLFꢌRUꢌPHWDOꢌSURWUXVLRQVꢌRIꢌꢈꢑꢀꢅꢌPPꢌꢏꢈꢑꢈꢈꢄꢌLQFKꢐꢌPD[LPXPꢌSHUꢌVLGHꢌDUHꢌQRWꢌLQFOXGHGꢑꢌꢌ
ꢃ5()(5(1&(6ꢃ
ꢃ-('(&ꢃ ꢃ-(,7$ꢃ
ꢌ06ꢎꢈꢀꢂꢌ
287/,1(ꢃ
9(56,21ꢃ
(8523($1ꢃ
352-(&7,21ꢃ
,668(ꢃ'$7(ꢃ
ꢃ,(&ꢃ
ꢆꢆꢎꢀꢂꢎꢂꢊꢌ
ꢈꢁꢎꢈꢂꢎꢀꢆꢌ
ꢌ627ꢀꢈꢇꢎꢀꢌ
ꢌꢈꢊꢄ(ꢈꢄꢌ
Fig 13. Package outline SOT108-1 (SO14)
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
10 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
6623ꢀꢇꢈꢃSODVWLFꢃVKULQNꢃVPDOOꢃRXWOLQHꢃSDFNDJHꢉꢃꢀꢇꢃOHDGVꢉꢃERG\ꢃZLGWKꢃꢎꢄꢁꢃPPꢃ
627ꢁꢁꢏꢍꢀꢃ
'ꢌ
(ꢌ
+ꢌ
$ꢌ
;ꢌ
Fꢌ
\ꢌ
Yꢌ 0ꢌ
$ꢌ
(ꢌ
=ꢌ
ꢇꢌ
ꢀꢃꢌ
4ꢌ
$ꢌ
ꢂꢌ
$ꢌ
ꢏ$ꢌꢌꢐꢌ
ꢁꢌ
$ꢌ
ꢀꢌ
SLQꢌꢀꢌLQGH[ꢌ
șꢌ
/ꢌ
Sꢌ
/ꢌ
ꢊꢌ
ꢀꢌ
GHWDLOꢌ;ꢌ
Zꢌ 0ꢌ
Eꢌ
Sꢌ
Hꢌ
ꢈꢌ
ꢂꢑꢅꢌ
ꢅꢌPPꢌ
VFDOHꢌ
',0(16,216ꢃꢅPPꢃDUHꢃWKHꢃRULJLQDOꢃGLPHQVLRQVꢆꢃ
$ꢃ
ꢅꢀꢆꢃ
ꢅꢀꢆꢃ
ꢅꢀꢆꢃ
81,7ꢃ
$ꢃ
$ꢃ
$ꢃ
Eꢃ
Fꢃ
'ꢃ
(ꢃ
Hꢃ
+ꢃ
/ꢃ
/ꢃ
4ꢃ
Yꢃ
ꢈꢑꢂꢌ
Zꢃ
ꢈꢑꢀꢁꢌ
\ꢃ
=ꢃ
șꢌ
Sꢃ
Sꢃ
ꢀꢃ
ꢂꢃ
ꢁꢃ
(ꢃ
PD[ꢄꢃ
Rꢌ
ꢈꢑꢂꢀꢌ ꢀꢑꢇꢈꢌ
ꢈꢑꢈꢅꢌ ꢀꢑꢄꢅꢌ
ꢈꢑꢁꢇꢌ ꢈꢑꢂꢈꢌ
ꢈꢑꢂꢅꢌ ꢈꢑꢈꢆꢌ
ꢄꢑꢃꢌ
ꢄꢑꢈꢌ
ꢅꢑꢃꢌ
ꢅꢑꢂꢌ
ꢊꢑꢆꢌ
ꢊꢑꢄꢌ
ꢀꢑꢈꢁꢌ
ꢈꢑꢄꢁꢌ
ꢈꢑꢆꢌ
ꢈꢑꢊꢌ
ꢀꢑꢃꢌ
ꢈꢑꢆꢌ
ꢇꢌ
PPꢌ
ꢂꢌ
ꢈꢑꢀꢌ
ꢈꢑꢂꢅꢌ
ꢈꢑꢄꢅꢌ
ꢀꢑꢂꢅꢌ
Rꢌ
ꢈꢌ
1RWHꢃ
ꢀꢑꢌ3ODVWLFꢌRUꢌPHWDOꢌSURWUXVLRQVꢌRIꢌꢈꢑꢂꢅꢌPPꢌPD[LPXPꢌSHUꢌVLGHꢌDUHꢌQRWꢌLQFOXGHGꢑꢌꢌ
ꢃ5()(5(1&(6ꢃ
ꢃ-('(&ꢃ ꢃ-(,7$ꢃ
ꢌ02ꢎꢀꢅꢈꢌ
287/,1(ꢃ
9(56,21ꢃ
(8523($1ꢃ
352-(&7,21ꢃ
,668(ꢃ'$7(ꢃ
ꢃ,(&ꢃ
ꢆꢆꢎꢀꢂꢎꢂꢊꢌ
ꢈꢁꢎꢈꢂꢎꢀꢆꢌ
ꢌ627ꢁꢁꢊꢎꢀꢌ
Fig 14. Package outline SOT337-1 (SSOP14)
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
11 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
76623ꢀꢇꢈꢃSODVWLFꢃWKLQꢃVKULQNꢃVPDOOꢃRXWOLQHꢃSDFNDJHꢉꢃꢀꢇꢃOHDGVꢉꢃERG\ꢃZLGWKꢃꢇꢄꢇꢃPPꢃ
627ꢇꢋꢂꢍꢀꢃ
'ꢌ
(ꢌ
$ꢌ
;ꢌ
Fꢌ
\ꢌ
+ꢌ
(ꢌ
Yꢌ 0ꢌ
$ꢌ
=ꢌ
ꢇꢌ
ꢀꢃꢌ
4ꢌ
ꢏ$ꢌꢌꢐꢌ
ꢁꢌ
$ꢌ
ꢂꢌ
$ꢌ
$ꢌ
ꢀꢌ
SLQꢌꢀꢌLQGH[ꢌ
șꢌ
/ꢌ
Sꢌ
/ꢌ
ꢀꢌ
ꢊꢌ
GHWDLOꢌ;ꢌ
Zꢌ 0ꢌ
Eꢌ
Sꢌ
Hꢌ
ꢈꢌ
ꢂꢑꢅꢌ
ꢅꢌPPꢌ
VFDOHꢌ
',0(16,216ꢃꢅPPꢃDUHꢃWKHꢃRULJLQDOꢃGLPHQVLRQVꢆꢃ
$ꢃ
ꢅꢀꢆꢃ
ꢅꢂꢆꢃ
ꢅꢀꢆꢃ
81,7ꢃ
PPꢌ
$ꢃ
ꢀꢃ
$ꢃ
ꢂꢃ
$ꢃ
ꢁꢃ
Eꢃ
Sꢃ
Fꢃ
'ꢃ
(ꢃ
Hꢃ
+ꢃ
/ꢃ
/ꢃ
Sꢃ
4ꢃ
Yꢃ
Zꢃ
\ꢃ
ꢈꢑꢀꢌ
=ꢃ
șꢌ
(ꢃ
PD[ꢄꢃ
Rꢌ
ꢈꢑꢀꢅꢌ ꢈꢑꢆꢅꢌ
ꢈꢑꢈꢅꢌ ꢈꢑꢇꢈꢌ
ꢈꢑꢁꢈꢌ
ꢈꢑꢀꢆꢌ
ꢈꢑꢂꢌ
ꢈꢑꢀꢌ
ꢅꢑꢀꢌ
ꢃꢑꢆꢌ
ꢃꢑꢅꢌ
ꢃꢑꢁꢌ
ꢄꢑꢄꢌ
ꢄꢑꢂꢌ
ꢈꢑꢊꢅꢌ
ꢈꢑꢅꢈꢌ
ꢈꢑꢃꢌ
ꢈꢑꢁꢌ
ꢈꢑꢊꢂꢌ
ꢈꢑꢁꢇꢌ
ꢇꢌ
ꢀꢑꢀꢌ
ꢈꢑꢄꢅꢌ
ꢀꢌ
ꢈꢑꢂꢌ ꢈꢑꢀꢁꢌ
ꢈꢑꢂꢅꢌ
Rꢌ
ꢈꢌ
1RWHVꢃ
ꢀꢑꢌ3ODVWLFꢌRUꢌPHWDOꢌSURWUXVLRQVꢌRIꢌꢈꢑꢀꢅꢌPPꢌPD[LPXPꢌSHUꢌVLGHꢌDUHꢌQRWꢌLQFOXGHGꢑꢌ
ꢂꢑꢌ3ODVWLFꢌLQWHUOHDGꢌSURWUXVLRQVꢌRIꢌꢈꢑꢂꢅꢌPPꢌPD[LPXPꢌSHUꢌVLGHꢌDUHꢌQRWꢌLQFOXGHGꢑꢌ
ꢃ5()(5(1&(6ꢃ
ꢃ-('(&ꢃ ꢃ-(,7$ꢃ
ꢌ02ꢎꢀꢅꢁꢌ
287/,1(ꢃ
9(56,21ꢃ
(8523($1ꢃ
352-(&7,21ꢃ
,668(ꢃ'$7(ꢃ
ꢃ,(&ꢃ
ꢆꢆꢎꢀꢂꢎꢂꢊꢌ
ꢈꢁꢎꢈꢂꢎꢀꢇꢌ
ꢌ627ꢃꢈꢂꢎꢀꢌ
Fig 15. Package outline SOT402-1 (TSSOP14)
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
12 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
'+94)1ꢀꢇꢈꢃSODVWLFꢃGXDOꢃLQꢍOLQHꢃFRPSDWLEOHꢃWKHUPDOꢃHQKDQFHGꢃYHU\ꢃWKLQꢃTXDGꢃIODWꢃSDFNDJHꢉꢃQRꢃOHDGVꢉ
ꢀꢇꢃWHUPLQDOVꢉꢃERG\ꢃꢂꢄꢎꢃ[ꢃꢁꢃ[ꢃꢋꢄꢌꢎꢃPPꢃꢃ
627ꢏꢐꢂꢍꢀ
%
$
(
'
$
$
ꢀ
F
GHWDLOꢌ;
WHUPLQDOꢌꢀ
LQGH[ꢌDUHD
&
WHUPLQDOꢌꢀ
LQGH[ꢌDUHD
H
ꢀ
Y
Z
&
&
$ %
\
\
&
ꢀ
H
E
ꢂ
ꢄ
/
ꢀ
ꢊ
ꢇ
(
K
H
ꢀꢃ
N
ꢀꢁ
ꢆ
'
K
;
N
ꢈ
ꢂ
ꢃꢌPP
Z
VFDOH
'LPHQVLRQVꢌꢏPPꢌDUHꢌWKHꢌRULJLQDOꢌGLPHQVLRQVꢐ
ꢏꢀꢐ
ꢏꢀꢐ
ꢏꢀꢐ
8QLW
$
$
E
F
'
'
K
(
(
H
H
N
/
Y
\
\
ꢀ
ꢀ
K
ꢀ
PD[
QRP
PLQ
ꢀ
ꢈꢑꢈꢅ ꢈꢑꢁꢈ
ꢈꢑꢈꢂ ꢈꢑꢂꢅ ꢈꢑꢂ ꢁꢑꢈ ꢀꢑꢅꢈ ꢂꢑꢅ ꢀꢑꢈꢈ ꢈꢑꢅ
ꢈꢑꢈꢈ ꢈꢑꢀꢇ ꢂꢑꢆ ꢀꢑꢁꢅ ꢂꢑꢃ ꢈꢑꢇꢅ
ꢁꢑꢀ ꢀꢑꢄꢅ ꢂꢑꢄ ꢀꢑꢀꢅ
ꢈꢑꢅ
ꢈꢑꢃ ꢈꢑꢀ ꢈꢑꢈꢅ ꢈꢑꢈꢅ ꢈꢑꢀ
ꢈꢑꢂ ꢈꢑꢁ
PP
ꢂ
1RWH
VRWꢂꢈꢆꢊꢅBSR
ꢀꢑꢌ3ODVWLFꢌRUꢌPHWDOꢌSURWUXVLRQVꢌRIꢌꢈꢑꢈꢊꢅꢌPPꢌPD[LPXPꢌSHUꢌVLGHꢌDUHꢌQRWꢌLQFOXGHGꢑꢌ
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ
,VVXHꢌGDWH
,(&
-('(&
-(,7$
ꢀꢅꢎꢈꢃꢎꢀꢈ
ꢀꢅꢎꢈꢅꢎꢈꢅ
627ꢊꢄꢂꢎꢀ
02ꢎꢂꢃꢀ
Fig 16. Package outline SOT762-1 (DHVQFN14)
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
13 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
16. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 12. Revision history
Document ID
74LV132 v.6
Modifications:
74LV132 v.5
Modifications:
Release date
20151209
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV132 v.5
• Type number 74LV132N (SOT27-1) removed.
20090702 Product data sheet
-
74LV132 v.4
• Table 6: the conditions for HIGH-level output voltage and LOW-level output voltage have been
changed.
74LV132 v.4
74LV132 v.3
74LV132 v.2
74LV132 v.1
20071112
20040415
19980428
19970204
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
74LV132 v.3
74LV132 v.2
74LV132 v.1
-
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
14 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
15 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV132
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 9 December 2015
16 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transfer characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics. . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 December 2015
Document identifier: 74LV132
相关型号:
74LV132PW-T
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
74LV132PW/T3
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, Gate
NXP
©2020 ICPDF网 联系我们和版权申明