74LV4060D-Q100 [NXP]
LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16;
| 型号： | 74LV4060D-Q100 |
| 厂家： | 
NXP |
| 描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV4060-Q100
14-stage binary ripple counter with oscillator
Rev. 1 — 25 July 2014
Product data sheet
1. General description
The 74LV4060-Q100 is a low-voltage Si-gate CMOS device and is pin and function
compatible with the 74HC4060-Q100; 74HCT4060-Q100.
The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three
oscillator terminals (RS, RTC and CTC). It has ten buffered outputs (Q3 to Q9 and Q11 to
Q13) and an overriding asynchronous master reset (MR). The oscillator configuration
allows design of either RC or crystal oscillator circuits. The oscillator can be replaced by
an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC)
floating.
The counter advances on the negative-going transition of RS. A HIGH-level on MR resets
the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of the other input conditions.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide operating voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications from 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 C
All active components on chip
RC or crystal oscillator configuration
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Applications
Control counters
Timers
Frequency dividers
Time-delay circuits
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV4060D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width SOT109-1
3.9 mm
74LV4060PW-Q100 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
5. Functional diagram
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ꢃ
57& &7&
56
ꢁꢁ
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05
ꢁꢉ
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4ꢁꢁ
4ꢁꢉ
4ꢁꢀ
ꢉ
ꢀ
ꢀꢀꢁDDLꢂꢃꢄ
Fig 1. Logic symbol
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&75ꢁꢂ
ꢀ
ꢇ
ꢀ
ꢇ
ꢎ*
&7&
ꢃ
ꢁꢈ
ꢁꢁ
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ꢄ
ꢄ
57&
56
ꢂ
ꢂ
ꢍ
$1'
ꢆ
ꢁꢁ
ꢁꢉ
ꢆ
ꢍ
05
ꢁꢂ
ꢁꢀ
ꢁꢄ
ꢁ
ꢁꢂ
ꢁꢀ
ꢁꢄ
ꢁ
&7
&7
&7ꢌ ꢌꢈ
ꢃ
&7ꢌ ꢌꢈ
ꢃ
ꢁꢁ
ꢁꢁ
ꢉ
ꢉ
ꢁꢀ
ꢀ
ꢁꢀ
ꢀ
ꢊDꢋ
ꢊEꢋ
ꢀꢀꢁDDLꢂꢃꢅ
Fig 2. IEC logic symbol
74LV4060_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
2 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
&7&
))ꢌ
ꢁ
))ꢌ
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57&
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&3
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4
4
4
4
4
05
05
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05
05
4ꢀ
4ꢃ
4ꢁꢁ
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Fig 3. Logic diagram
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57&
ꢃ
&7&
56
ꢁꢁ
&3
05
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05
ꢁꢉ
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ꢇ
ꢄ
ꢂ
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ꢁꢂ
ꢁꢀ
ꢁꢄ
ꢁ
ꢉ
ꢀ
ꢀꢀꢁDDLꢁꢁꢆ
Fig 4. Functional diagram
6. Pinning information
6.1 Pinning
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ꢁ
ꢉ
ꢀ
ꢂ
ꢄ
ꢆ
ꢇ
ꢅ
ꢁꢆ
9
4ꢁꢁ
4ꢁꢉ
4ꢁꢀ
4ꢄ
&&
ꢁꢄ
ꢁꢂ
ꢁꢀ
ꢁꢉ
ꢁꢁ
ꢁꢈ
ꢃ
4ꢃ
4ꢇ
4ꢅ
05
56
4ꢂ
4ꢆ
4ꢀ
57&
&7&
*1'
DDDꢇꢀꢁꢂꢁꢈꢃ
Fig 5. Pin configuration
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
3 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
6.2 Pin description
Table 2.
Symbol
Q11 to Q13
Q3 to Q9
GND
Pin description
Pin
Description
counter output
counter output
ground (0 V)
1, 2, 3
7, 5, 4, 6, 14, 13, 15
8
CTC
9
external capacitor connection
external resistor connection
clock input/oscillator pin
master reset
RTC
10
11
12
16
RS
MR
VCC
supply voltage
7. Functional description
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ꢉ
ꢂ
ꢅ
ꢁꢆ
ꢀꢉ
ꢆꢂ
ꢁꢉꢅ
ꢉꢄꢆ
ꢄꢁꢉ
ꢁꢈꢉꢂ ꢉꢈꢂꢅ ꢂꢈꢃꢆ ꢅꢁꢃꢉ ꢁꢆꢀꢅꢂ
56
05
4ꢀ
4ꢂ
4ꢄ
4ꢆ
4ꢇ
4ꢅ
4ꢃ
4ꢁꢁ
4ꢁꢉ
4ꢁꢀ
ꢀꢀꢁDDLꢁꢁꢄ
Fig 6. Timing diagram
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
4 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
50
25
50
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C
SO16 package
[2]
[3]
-
-
500
400
mW
mW
TSSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] tot derates linearly with 8 mW/K above 70 C.
P
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max Unit
[1]
supply voltage
1.0
3.3
5.5
VCC
VCC
V
V
V
VI
input voltage
0
-
-
-
-
-
-
-
VO
output voltage
0
Tamb
t/V
ambient temperature
input transition rise and fall rate
in free air
40
+125 C
500 ns/V
200 ns/V
100 ns/V
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
50
ns/V
[1] The 74LV4060-Q100 is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); DC characteristics are guaranteed from
CC = 1.2 V to VCC = 5.5 V.
V
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
5 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
10. Static characteristics
Table 5.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
MR input
input voltage
VCC = 1.2 V
0.9
1.4
-
-
-
-
-
-
-
-
0.9
1.4
-
-
-
-
V
V
V
V
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
RS input
2.0
2.0
0.7VCC
0.7VCC
VCC = 1.2 V
1.0
1.6
-
-
-
-
-
-
-
-
1.0
1.6
-
-
-
-
V
V
V
V
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR input
2.4
2.4
0.8VCC
0.8VCC
VIL
LOW-level
input voltage
VCC = 1.2 V
-
-
-
-
-
-
-
-
0.3
0.6
-
-
-
-
0.3
0.6
V
V
V
V
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
RS input
0.8
0.8
0.3VCC
0.3VCC
V
CC = 1.2 V
-
-
-
-
-
-
-
-
0.2
0.4
-
-
-
-
0.2
0.4
V
V
V
V
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
0.5
0.5
VCC = 4.5 V to 5.5 V
0.2VCC
0.2VCC
VOH
HIGH-level
output voltage
RTC output; RS = MR = GND
VCC = 1.2 V; IO = 3.4 mA
VCC = 2.0 V; IO = 3.4 mA
VCC = 2.7 V; IO = 3.4 mA
VCC = 3.0 V; IO = 3.4 mA
VCC = 4.5 V; IO = 3.4 mA
RTC output; RS = MR = VCC
VCC = 1.2 V; IO = 0.8 mA
VCC = 2.0 V; IO = 0.8 mA
VCC = 2.7 V; IO = 0.8 mA
VCC = 3.0 V; IO = 0.8 mA
VCC = 4.5 V; IO = 0.8 mA
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
2.40
-
-
2.82
-
-
2.20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
2.40
-
-
2.82
-
-
2.20
-
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
6 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
Table 5.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOH
HIGH-level
output voltage
RTC output; RS = MR = GND
VCC = 1.2 V; IO = 100 A
VCC = 2.0 V; IO = 100 A
VCC = 2.7 V; IO = 100 A
VCC = 3.0 V; IO = 100 A
VCC = 4.5 V; IO = 100 A
RTC output; RS = MR = VCC
VCC = 1.2 V; IO = 100 A
VCC = 2.0 V; IO = 100 A
VCC = 2.7 V; IO = 100 A
VCC = 3.0 V; IO = 100 A
VCC = 4.5 V; IO = 100 A
CTC output; RS = VIH and MR = VIL
VCC = 1.2 V; IO = 3.8 mA
VCC = 2.0 V; IO = 3.8 mA
VCC = 2.7 V; IO = 3.8 mA
VCC = 3.0 V; IO = 3.8 mA
VCC = 4.5 V; IO = 3.8 mA
except RTC output; VI = VIH or VIL
VCC = 1.2 V; IO = 100 A
VCC = 2.0 V; IO = 100 A
VCC = 2.7 V; IO = 100 A
VCC = 3.0 V; IO = 100 A
VCC = 4.5 V; IO = 100 A
1.0
1.8
-
1.2
2.0
-
-
-
-
-
-
1.0
1.8
-
-
-
-
-
-
V
V
V
V
V
2.8
-
3.0
-
2.8
-
1.0
1.8
-
1.2
2.0
-
-
-
-
-
-
1.0
1.8
-
-
-
-
-
-
V
V
V
V
V
2.8
-
3.0
-
2.8
-
-
1.2
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
2.40
-
-
2.82
-
-
2.20
-
1.0
1.8
-
1.2
2.0
-
-
-
-
-
-
1.0
1.8
-
-
-
-
-
-
V
V
V
V
V
2.8
-
3.0
-
2.8
-
except RTC and CTC outputs;
VI = VIH or VIL
VCC = 1.2 V; IO = 6 mA
VCC = 2.0 V; IO = 6 mA
VCC = 2.7 V; IO = 6 mA
VCC = 3.0 V; IO = 6 mA
VCC = 4.5 V; IO = 6 mA
RTC output; RS = VCC and MR = GND
VCC = 1.2 V; IO = 3.4 mA
VCC = 2.0 V; IO = 3.4 mA
VCC = 2.7 V; IO = 3.4 mA
VCC = 3.0 V; IO = 3.4 mA
VCC = 4.5 V; IO = 3.4 mA
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
2.40
-
-
2.82
-
-
2.20
-
VOL
LOW-level
output voltage
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
0.25
-
-
0.40
-
-
0.50
-
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
7 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
Table 5.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOL
LOW-level
output voltage
RTC output; RS = VCC and MR = GND
VCC = 1.2 V; IO = 100 A
VCC = 2.0 V; IO = 100 A
VCC = 2.7 V; IO = 100 A
VCC = 3.0 V; IO = 100 A
VCC = 4.5 V; IO = 100 A
CTC output; RS = VIH and MR = VIL
VCC = 1.2 V; IO = 3.8 mA
VCC = 2.0 V; IO = 3.8 mA
VCC = 2.7 V; IO = 3.8 mA
VCC = 3.0 V; IO = 3.8 mA
VCC = 4.5 V; IO = 3.8 mA
except RTC output; VI = VIH or VIL
VCC = 1.2 V; IO = 100 A
VCC = 2.0 V; IO = 100 A
VCC = 2.7 V; IO = 100 A
VCC = 3.0 V; IO = 100 A
VCC = 4.5 V; IO = 100 A
-
-
-
-
-
0
0
-
0.2
0.2
-
-
-
-
-
-
0.2
0.2
-
V
V
V
V
V
0
-
0.2
-
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
-
-
-
-
0.25
-
-
0.40
-
-
0.50
-
-
-
-
-
-
0
0
-
0.2
0.2
-
-
-
-
-
-
0.2
0.2
-
V
V
V
V
V
0
-
0.2
-
0.2
-
except RTC and CTC output; VI = VIH or
VIL
VCC = 1.2 V; IO = 6 mA
VCC = 2.0 V; IO = 6 mA
VCC = 2.7 V; IO = 6 mA
VCC = 3.0 V; IO = 6 mA
VCC = 4.5 V; IO = 6 mA
VCC = 5.5 V; VI = VCC or GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
-
-
0.40
-
-
0.50
-
V
0.25
V
-
-
-
V
-
-
V
II
input leakage
current
1.0
1.0
A
ICC
supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A
VCC = 5.5 V; VI = VCC or GND; IO = 0 A
-
-
-
-
-
-
20
-
-
-
-
160
80
A
A
A
ICC
additional
VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V;
500
850
supply current IO = 0 A
CI
input
-
3.5
-
-
-
pF
capacitance
[1] All typical values are measured at Tamb = 25 C.
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
8 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
11. Dynamic characteristics
Table 6.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay RS to Q3; see Figure 7 and
Figure 9
VCC = 1.2 V
-
-
-
-
-
-
180
52
42
29
33
24
-
-
-
-
-
-
-
-
105
83
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
84
66
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
53
39
66
49
Qn to Qn+1; see Figure 8 and
Figure 9
VCC = 1.2 V
-
-
-
-
-
-
40
14
10
6
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
23
16
-
29
20
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
8
13
9
16
11
6
tPHL
HIGH to LOW
MR to Qn; see Figure 8 and
propagation delay Figure 9
VCC = 1.2 V
-
-
-
-
-
-
100
29
24
16
19
14
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
46
39
-
58
49
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
RS HIGH or LOW; see Figure 7
VCC = 2.0 V
[3]
[4]
31
23
39
29
tW
pulse width
34
25
20
16
9
6
5
4
-
-
-
-
38
30
24
20
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR HIGH; see Figure 9
VCC = 2.0 V
34
25
20
16
10
8
-
-
-
-
38
30
24
20
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
4
74LV4060_Q100
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Product data sheet
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9 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
Table 6.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
trec
recovery time
MR to RS; see Figure 9
VCC = 2.0 V
29
26
18
12
18
16
11
7
-
-
-
-
37
32
23
15
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
RS; see Figure 7
VCC = 2.0 V
fmax
maximum
frequency
14
19
-
40
70
-
-
-
-
-
-
9
12
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
pF
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
99
[3]
[4]
[5]
24
30
-
90
15
19
-
100
40
CPD
power dissipation VI = GND to VCC
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
.
[3] Typical value measured at VCC = 3.3 V.
[4] Typical value measured at VCC = 5.0 V.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74LV4060_Q100
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Product data sheet
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10 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
12. Waveforms
ꢁꢐI
PD[
9
,
56ꢌLQSXW
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9
0
W
W
:
W
3+/
3/+
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2+
9
4QꢌRXWSXW
0
9
2/
DDDꢇꢀꢁꢉꢊꢃꢁ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the clock (RS) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum frequency
9
2+
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9
0
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2/
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0
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9
2/
ꢀꢀꢁDDLꢁꢉꢀ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the output Qn to output Qn+1 propagation delays
74LV4060_Q100
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Product data sheet
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11 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
9
,
05ꢌLQSXW
*1'
9
0
W
:
W
UHF
9
,
56ꢌLQSXW
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9
0
W
3+/
9
2+
9
4QꢌRXWSXW
0
9
2/
ꢀꢀꢁDDLꢁꢁꢊ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (RS) recovery time
Table 7.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
2.7 V to 3.6 V
4.5 V
0.5VCC
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ꢉꢌ[ꢌ9
&&
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9
&&
5
5
/
9
9
2
,
38/6(ꢌ
*(1(5$725
'ꢑ8ꢑ7ꢑ
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Test data is given in Table 8.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 10. Test circuit for measuring switching times
74LV4060_Q100
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NXP Semiconductors
14-stage binary ripple counter with oscillator
W
:
9
,
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9
9
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W
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Fig 11. Input pulse definition
Table 8.
Test data
Supply voltage
VCC
Input
VI
Load
CL
S1
tr, tf
RL
tPLH, tPHL
open
open
open
< 2.7 V
VCC
2.7 V
VCC
2.5 ns
2.5 ns
2.5 ns
50 pF
1 k
1 k
1 k
2.7 V to 3.6 V
4.5 V
15 pF, 50 pF
50 pF
13. Typical forward transconductance
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gfs = IO / VI at VO is constant; MR = LOW.
Tamb = 25 C
See Figure 13.
Fig 12. Test setup for measuring forward
transconductance
Fig 13. Typical forward transconductance as function
of the supply voltage
74LV4060_Q100
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NXP Semiconductors
14-stage binary ripple counter with oscillator
14. RC oscillator
14.1 Timing component limitations
The oscillator frequency is mainly determined by Rt Ct, provided R2 2Rt and R2 C2
is much less than Rt Ct. The function of R2 is to minimize the influence of the forward
voltage across the input protection diodes on the frequency. The stray capacitance C2
should be kept as small as possible. In consideration of accuracy, Ct must be larger than
the inherent stray capacitance. Rt must be larger than the ‘ON’ resistance in series with it,
which typically is 280 at VCC = 1.2 V, 130 at VCC = 2.0 V and 100 at VCC 3.0 V. The
recommended values for these components to maintain agreement with the typical
oscillation formula are: Ct > 50 pF, up to any practical value, 10 k < Rt < 1 M. In order
to avoid start-up problems, Rt 1 k.
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=
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Fig 14. Example of an RC oscillator
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Rt curve: Ct = 1 nF; R2 = 2 Rt
VCC = 1.2 V to 3.6 V; Tamb = 25 C
Ct curve: Rt = 100 k; R2 = 200 k
Fig 15. RC oscillator frequency as a function of Rt
Fig 16. RC oscillator frequency as a function of Ct
74LV4060_Q100
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NXP Semiconductors
14-stage binary ripple counter with oscillator
14.2 Typical crystal oscillator circuit
In Figure 17, R2 is the power limiting resistor. For starting and maintaining oscillation, a
minimum transconductance is necessary, so R2 must not be too large. A practical value
for R2 is 2.2 k.
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Fig 17. External components connection for a typical crystal oscillator
74LV4060_Q100
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NXP Semiconductors
14-stage binary ripple counter with oscillator
15. Package outline
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Fig 18. Package outline SOT109-1 (SO16)
74LV4060_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
16 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
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Fig 19. Package outline SOT403-1 (TSSOP16)
74LV4060_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors
14-stage binary ripple counter with oscillator
16. Abbreviations
Table 9.
Acronym
CMOS
DUT
Abbreviations
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 10. Revision history
Document ID
Release date
20140725
Data sheet status
Change notice
Supersedes
74LV4060_Q100 v.1
Product data sheet
-
-
74LV4060_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
18 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
18.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
19 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
20 of 21
74LV4060-Q100
NXP Semiconductors
14-stage binary ripple counter with oscillator
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical forward transconductance. . . . . . . . . 13
8
9
10
11
12
13
14
14.1
14.2
RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing component limitations . . . . . . . . . . . . . 14
Typical crystal oscillator circuit . . . . . . . . . . . . 15
15
16
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 July 2014
Document identifier: 74LV4060_Q100
相关型号：
74LV4060PW-Q100
LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
NXP
74LV4060PWDH-T
IC LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, Counter
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