74LV4094PW,118 [NXP]
74LV4094 - 8-stage shift-and-store bus register TSSOP 16-Pin;
| 型号： | 74LV4094PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LV4094 - 8-stage shift-and-store bus register TSSOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV4094
8-stage shift-and-store bus register
Rev. 02 — 29 June 2006
Product data sheet
1. General description
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and function compatible
with 74HC4094, 74HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage latch associated with
each stage for strobing data from the serial input (D) to the parallel buffered 3-state
outputs (QP0 to QP7). The parallel outputs may be connected directly to the common bus
lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift
register is transferred to the storage register when the strobe input (STR) is HIGH. Data in
the storage register appears at the outputs whenever the output enable input (OE) signal
is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of
74LV4094 devices. Data is available at QS1 on the positive-going clock edges to allow
high-speed operation in cascaded systems in which the clock rise time is fast. The same
serial information is available at QS2 on the next negative going clock edge and is for
cascading 74LV4094 devices when the clock rise time is slow.
2. Features
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C
I Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25 °C
I ESD protection:
N HBM EIA/JESD22-A114-C exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
I Serial-to-parallel data conversion
I Remote control holding register
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
4. Ordering information
Table 1.
Type number Package
Temperature
range
Ordering information
Name
Description
Version
74LV4094N
74LV4094D
74LV4094DB
−40 °C to +125 °C DIP16
−40 °C to +125 °C SO16
−40 °C to +125 °C SSOP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
74LV4094PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
5. Functional diagram
3
1
1
C2
15
EN3
CP
STR
QS1
QS2
QP0
QP1
QP2
9
SRG8
C1/
3
2
10
4
4
5
1D
2D
3
5
6
6
2
D
7
QP3
QP4
QP5
QP6
QP7
7
14
13
12
11
9
14
13
12
11
OE
15
10
001aaf112
001aaf111
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D
2
3
8-STAGE SHIFT
REGISTER
QS2
QS1
10
9
CP
STR
OE
8-BIT STORAGE
REGISTER
1
15
3-STATE OUTPUTS
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
14 13 12 11
4
5
6
7
001aaf119
Fig 3. Functional diagram
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
2 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
STAGE 0
STAGES 1 TO 6
STAGE 7
D
QS1
QS2
D
Q
D
Q
D
Q
CP
CP FF
7
FF
0
D
Q
CP
CP
CP
latch
D
Q
D
Q
CP
CP
latch
latch
STR
OE
QP0
QP1 QP2 QP3 QP4 QP5 QP6
QP7
001aaf118
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
74LV4094
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
STR
D
V
CC
OE
CP
QP4
QP5
QP6
QP7
QS2
QS1
QP0
QP1
QP2
QP3
GND
001aaf120
Fig 5. Pin configuration DIP16, SO16 and (T)SSOP16
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
3 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
6.2 Pin description
Table 2.
Symbol
STR
D
Pin description
Pin
1
Description
data strobe input
data serial input
2
CP
3
clock input (edge triggered LOW-to-HIGH)
data parallel output 0
data parallel output 1
data parallel output 2
data parallel output 3
ground (0 V)
QP0
QP1
QP2
QP3
GND
QS1
QS2
QP7
QP6
QP5
QP4
OE
4
5
6
7
8
9
data serial output 1
data serial output 2
data parallel output 7
data parallel output 6
data parallel output 5
data parallel output 4
output enable input
supply voltage
10
11
12
13
14
15
16
VCC
7. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; n.c. = no change;
↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition.
Input
Parallel output
Serial output
QS1[1]
QS6
CP
↑
OE
L
STR
X
D
X
X
X
L
QP0
Z
QPn
Z
QS2
n.c.
↓
L
X
Z
Z
n.c.
QP7
n.c.
↑
H
H
H
H
L
n.c.
L
n.c.
QS6
↑
H
QPn−1
QPn−1
n.c.
QS6
n.c.
↑
H
H
H
H
QS6
n.c.
↓
H
n.c.
n.c.
QP7
[1] QS6 = the information in the 7th register stage is transferred to the 8th register stage and QS1, QS2 clock edge.
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
4 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
Z-state
Z-state
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Fig 6. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
−0.5 +7.0
VCC
IIK
supply voltage
V
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
-
-
-
-
±20 mA
±50 mA
±25 mA
IOK
IO
[1]
ICC
IGND
Tstg
Ptot
quiescent supply current
ground current
50
mA
−50 mA
storage temperature
total power dissipation
DIP16 package
−65 +150 °C
Tamb = −40 °C to +125 °C
[2]
[3]
[4]
-
-
-
750 mW
500 mW
400 mW
SO16 package
(T)SSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[3] SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
[4] (T)SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 °C.
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
5 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
9. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
3.6
Unit
V
[1]
VCC
VI
supply voltage
1.0
3.3
input voltage
0
-
-
-
-
-
-
VCC
VCC
V
VO
output voltage
0
V
Tamb
tr, tf
ambient temperature
input rise and fall time
in free air
−40
+125 °C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
-
-
-
500
200
100
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed
function down to VCC = 1.0 V (with input levels GND or VCC).
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-state input voltage
VCC = 1.2 V
VCC
0.6
-
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
VCC = 2.7 V to 3.6 V
2.0
-
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 1.2 V
-
-
-
0.4
GND
0.6
0.8
VCC = 2.0 V
-
-
VCC = 2.7 V to 3.6 V
VOH
VI = VIH or VIL; all pins
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
VI = VIH or VIL; pins QPn
IO = −6 mA; VCC = 3.0 V
VI = VIH or VIL; all pins
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
VI = VIH or VIL; pins QPn
IO = 6 mA; VCC = 3.0 V
VI = VCC or GND; VCC = 3.6 V
VI = VIH or VIL; VO = VCC or GND;
-
1.2
2.0
2.7
3.0
-
-
-
-
V
V
V
V
1.8
2.5
2.8
2.40
2.82
-
V
VOL
LOW-state output voltage
-
-
-
-
0
0
0
0
-
V
V
V
V
0.2
0.2
0.2
-
-
-
0.25
0.40
1.0
5
V
ILI
input leakage current
-
-
µA
µA
IOZ
OFF-state output current
VCC = 3.6 V
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
6 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICC
∆ICC
Ci
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
20.0
µA
V
CC = 3.6 V
per input; VI = VCC − 0.6 V;
CC = 2.7 V to 3.6 V
additional quiescent supply
current
-
-
-
-
500
3.5
µA
V
input capacitance
pF
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 1.2 V
VCC
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
VCC = 2.7 V to 3.6 V
2.0
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 1.2 V
-
-
-
GND
0.6
0.8
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VOH
VI = VIH or VIL; all pins
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
VI = VIH or VIL; pins QPn
IO = −6 mA; VCC = 3.0 V
VI = VIH or VIL; all pins
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
VI = VIH or VIL; pins QPn
IO = 6 mA; VCC = 3.0 V
VI = VCC or GND; VCC = 3.6 V
VI = VIH or VIL; VO = VCC or GND;
-
-
-
-
-
-
-
-
-
V
V
V
V
1.8
2.5
2.8
2.20
-
-
V
VOL
LOW-state output voltage
-
-
-
-
-
-
-
-
-
V
V
V
V
0.2
0.2
0.2
-
-
-
-
-
-
0.50
1.0
10
V
ILI
input leakage current
µA
µA
IOZ
OFF-state output current
V
CC = 3.6 V
VI = VCC or GND; IO = 0 A;
CC = 3.6 V
per input; VI = VCC − 0.6 V;
ICC
quiescent supply current
-
-
-
-
160
850
µA
µA
V
∆ICC
additional quiescent supply
current
VCC = 2.7 V to 3.6 V
[1] All typical values are measured at Tamb = 25 °C.
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
7 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Tamb = −40 °C to +85 °C[1]
propagation delay CP to QS1
Parameter
Conditions
Min
Typ
Max Unit
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
see Figure 7
VCC = 1.2 V
-
-
-
-
-
90
31
23
17
14
-
ns
ns
ns
ns
ns
VCC = 2.0 V
58
43
34
-
VCC = 2.7 V
[2]
[2]
[2]
[2]
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
see Figure 7
propagation delay CP to QS2
propagation delay CP to QPn
propagation delay STR to QPn
VCC = 1.2 V
-
-
-
-
-
80
27
20
14
13
-
ns
ns
ns
ns
ns
VCC = 2.0 V
51
38
30
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
see Figure 7
VCC = 1.2 V
-
-
-
-
-
115
39
-
ns
ns
ns
ns
ns
VCC = 2.0 V
75
55
44
-
VCC = 2.7 V
29
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
see Figure 8
22
18
VCC = 1.2 V
-
-
-
-
-
105
36
-
ns
ns
ns
ns
ns
VCC = 2.0 V
68
50
40
-
VCC = 2.7 V
26
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
see Figure 9
20
17
tPZH, tPZL
3-state output enable time OE to QPn
3-state output disable time OE to QPn
VCC = 1.2 V
-
-
-
-
100
34
-
ns
ns
ns
ns
VCC = 2.0 V
65
48
38
VCC = 2.7 V
25
[2]
VCC = 3.0 V to 3.6 V
see Figure 9
19
tPHZ, tPLZ
VCC = 1.2 V
-
-
-
-
65
24
18
14
-
ns
ns
ns
ns
VCC = 2.0 V
40
32
26
VCC = 2.7 V
[2]
VCC = 3.0 V to 3.6 V
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
8 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tW
pulse width CP HIGH or LOW
see Figure 7
VCC = 2.0 V
34
25
20
9
6
5
-
-
-
ns
ns
ns
VCC = 2.7 V
[2]
[2]
VCC = 3.0 V to 3.6 V
see Figure 8
tW
pulse width STR HIGH
set-up time D to CP
VCC = 2.0 V
34
25
20
9
6
5
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
tsu
VCC = 1.2 V
-
25
9
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
22
16
13
VCC = 2.7 V
6
[2]
[2]
[2]
[2]
VCC = 3.0 V to 3.6 V
see Figure 8
5
tsu
set-up time CP to STR
VCC = 1.2 V
-
50
17
13
10
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
43
31
25
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 10
VCC = 1.2 V
th
hold time D to CP
-
−10
−4
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5
5
5
VCC = 2.7 V
−3
VCC = 3.0 V to 3.6 V
see Figure 10
VCC = 1.2 V
−2
th
hold time D to STR
-
−25
−9
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5
5
5
VCC = 2.7 V
−6
VCC = 3.0 V to 3.6 V
see Figure 7
−5
fmax
maximum input clock frequency
VCC = 2.0 V
14
19
24
-
52
70
87
95
83
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
VCC = 2.7 V
[2]
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.3 V
[3][4]
CPD power dissipation capacitance
Tamb = −40 °C to +125 °C
-
tPHL, tPLH
propagation delay CP to QS1
see Figure 7
VCC = 1.2 V
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
70
51
41
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
9 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tPHL, tPLH
propagation delay CP to QS2
see Figure 7
VCC = 1.2 V
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
61
45
36
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
VCC = 1.2 V
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
propagation delay CP to QPn
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
90
66
53
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
VCC = 1.2 V
propagation delay STR to QPn
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
82
60
48
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 9
VCC = 1.2 V
3-state output enable time OE to QPn
3-state output disable time OE to QPn
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
77
56
45
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 9
VCC = 1.2 V
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
49
37
30
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
VCC = 2.0 V
tW
tW
tsu
pulse width CP HIGH or LOW
pulse width STR HIGH
set-up time D to CP
41
30
24
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
VCC = 2.0 V
41
30
24
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
VCC = 1.2 V
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
26
19
15
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
10 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tsu
set-up time CP to STR
see Figure 8
VCC = 1.2 V
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
51
38
30
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 10
VCC = 1.2 V
th
hold time D to CP
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5
5
5
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 10
VCC = 1.2 V
th
hold time D to STR
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5
5
5
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
VCC = 2.0 V
fmax
maximum input clock frequency
12
16
20
-
-
-
-
-
-
MHz
MHz
MHz
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at Tamb = 25 °C.
[2] Typical value measured at VCC = 3.3 V.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
∑(CL × VCC2 × fo) = sum of the outputs.
[4] The condition is VI = GND to VCC
.
74LV4094_2
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Product data sheet
Rev. 02 — 29 June 2006
11 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
12. Waveforms
1/f
max
V
I
CP input
QPn, QS1 output
QS2 output
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
M
V
OL
t
t
PHL
PLH
V
OH
V
M
V
OL
001aaf113
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. Propagation delay clock (CP) to output (QPn, QS1, QS2), clock pulse width and
maximum clock frequency
V
I
CP input
STR input
QPn output
V
M
GND
t
t
h
su
V
I
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
M
V
OL
001aaf114
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 8. Strobe (STR) to output (QPn) propagation delays and the strobe pulse width and
the clock set-up and hold times for strobe input
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
12 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
V
I
V
OE input
GND
M
t
PZL
t
PLZ
V
CC
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aaf116
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 9. 3-state output enable and disable times for input OE
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
D input
M
GND
V
OH
V
QPn, QS1, QS2 output
M
V
OL
001aaf115
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 10. Data set-up and hold times for the data input (D)
Table 8.
Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
VY
1.2 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.1 × VCC
VOL + 0.1 × VCC
VOL + 0.3 V
VOL + 0.3 V
VOH + 0.1 × VCC
VOH + 0.1 × VCC
VOH + 0.3 V
VOH + 0.3 V
2.0 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
13 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions test circuit:
RL = load resistor.
CL = load capacitance.
RT = Termination resistance should be equal to output impedance of Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 11. Load circuitry for measuring switching times
Table 9.
Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL
tPLH, tPHL
open
< 2.7 V
VCC
≤ 2.5 ns 50 pF
1 kΩ
1 kΩ
GND
GND
2 × VCC
2 × VCC
2.7 V to 3.6 V
2.7 V ≤ 2.5 ns 50 pF
open
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
14 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 12. Package outline SOT38-4 (DIP16)
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
15 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
16 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 14. Package outline SOT338-1 (SSOP16)
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
17 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
18 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
74LV4094_2
Modifications:
Release date
20060629
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV4094_1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
• Section 4: Added type numbers 74LV4094DB and 74LV4094PW
74LV4094_1
19980623
Product specification
-
-
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
19 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
malfunction of a Philips Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
20 of 21
74LV4094
Philips Semiconductors
8-stage shift-and-store bus register
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 29 June 2006
Document identifier: 74LV4094_2
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