74LVC109D,118 [NXP]
74LVC109 - Dual JK(not) flip-flop with set and reset; positive-edge trigger SOP 16-Pin;
| 型号： | 74LVC109D,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC109 - Dual JK(not) flip-flop with set and reset; positive-edge trigger SOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
2004 Mar 18
Supersedes data of 1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
FEATURES
DESCRIPTION
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74LVC109A is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC109A is a dual positive edge triggered
JK flip-flop featuring individual J and K inputs, clock (CP)
inputs, set (SD) and reset (RD) inputs and complementary
Q and Q outputs.
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation. The JK design allows operation as a D-type
flip-flop by tying the J and K inputs together.
• Specified from −40 to +85 °C and −40 to +125 °C.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
3.8
UNIT
tPHL/tPLH
propagation delay nCP to nQ
and nCP to nQ
CL = 50 pF; RL = 500 Ω; VCC = 3.3 V
ns
ns
ns
propagation delay nSD to nQ
and nRD to nQ
CL = 50 pF; RL = 500 Ω; VCC = 3.3 V
CL = 50 pF; RL = 500 Ω; VCC = 3.3 V
CL = 50 pF; RL = 500 Ω; VCC = 3.3 V
3.2
3.5
propagation delay nSD to nQ
and nRD to nQ
fmax
CI
maximum clock frequency
input capacitance
330
5.0
23
MHz
pF
CPD
power dissipation capacitance per notes 1 and 2
flip-flop
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2004 Mar 18
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
FUNCTION TABLE
See note 1.
INPUT
nCP
OUTPUT
OPERATING MODES
nSD
nRD
nJ
nK
nQ
nQ
Asynchronous set
Asynchronous reset
Undetermined
Toggle
L
H
L
H
L
X
X
X
↑
X
X
X
h
l
X
X
X
l
H
L
L
H
H
q
L
H
q
H
H
H
H
H
H
H
H
Load 0 (reset)
Load 1 (set)
↑
l
L
H
L
↑
h
l
h
h
H
q
Hold no change
↑
q
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH
CP transition;
X = don’t care;
↑ = LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74LVC109D
74LVC109DB
74LVC109PW
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
16
16
16
SO16
plastic
plastic
plastic
SOT109-1
SOT338-1
SOT403-1
SSOP16
TSSOP16
2004 Mar 18
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
PINNING
PIN
SYMBOL
DESCRIPTION
asynchronous reset input (active LOW)
1
1RD
1J
2
synchronous input
3
1K
synchronous input
4
1CP
1SD
1Q
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
5
6
7
1Q
complement flip-flop output
ground (0 V)
8
GND
2Q
9
complement flip-flop output
true flip-flop output
10
11
12
13
14
15
16
2Q
2SD
2CP
2K
asynchronous set input (active LOW)
clock input (LOW-to-HIGH; edge-triggered)
synchronous input
2J
synchronous input
2RD
VCC
asynchronous reset input (active LOW)
supply voltage
handbook, halfpage
V
1RD
1
2
3
16
15
14
13
12
11
10
9
CC
2RD
2J
5 11
1SD 2SD
SD
handbook, halfpage
1J
1K
1Q
2Q
6
2
14
4
1J
2J
1CP
2CP
J
Q
2K
1CP
4
10
109
CP
2CP
2SD
2Q
5
1SD
1Q
12
FF
1Q
2Q
7
9
3
13
1K
2K
Q
K
6
7
8
RD
1Q
1RD 2RD
1 15
2Q
GND
MNA858
MNA855
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Logic symbol.
2004 Mar 18
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
handbook, halfpage
1SD
5
SD
1Q
1Q
1J
2
4
3
Q
J
6
7
1CP
1K
CP FF1
Q
5
11
14
handbook, halfpage
S
S
K
2
4
3
1
1J
1J
6
7
10
9
RD
12
13
15
1RD
2SD
C1
C1
1
1K
R
1K
R
11
SD
2Q
2Q
2J
10
9
14
12
13
J
Q
(a)
(b)
MNA856
2CP
2K
CP FF2
K
Q
RD
2RD
15
MNA857
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
Q
Q
C
C
C
C
C
C
C
K
J
C
S
R
C
C
CP
MNA859
Fig.5 Logic diagram (one flip-flop).
5
2004 Mar 18
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
for maximum speed performance 2.7
V
for low-voltage applications
1.2
0
3.6
5.5
VCC
+125
20
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
tr, tf
ambient temperature
input rise and fall times
in free air
−40
0
°C
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
output diode current
output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
VO
−0.5
−
VCC + 0.5
±50
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 to VCC
mA
mA
°C
ICC, IGND
Tstg
Ptot
−
±100
+150
500
−65
−
Tamb = −40 to +125 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
2004 Mar 18
6
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to 85 °C; note 1
VIH
VIL
HIGH-level input
voltage
1.2
VCC
−
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
V
V
V
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −12 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.2 VCC
−
−
−
−
V
V
V
V
CC − 0.5
CC − 0.6
CC − 0.8
−
−
−
3.0
3.0
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
−
GND
−
0.2
0.4
0.55
±5
V
V
IO = 24 mA
3.0
−
V
ILI
input leakage current VI = 5.5 V or GND
3.6
±0.1
0.1
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0 A
3.6
10
∆ICC
additional quiescent
supply current per
input pin
VI = VCC − 0.6 V;
IO = 0 A
2.7 to 3.6
−
5
500
µA
2004 Mar 18
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
TEST CONDITIONS
OTHER VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to 125 °C
VIH
HIGH-level input
voltage
1.2
VCC
−
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
V
V
V
VIL
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −12 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.3
−
CC − 0.65 −
CC − 0.75 −
−
−
−
−
V
V
V
V
3.0
3.0
CC − 1.0
−
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
−
−
−
−
−
−
0.3
0.6
0.8
±20
40
V
V
IO = 24 mA
3.0
V
ILI
input leakage current VI = 5.5 V or GND
3.6
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0 A
3.6
∆ICC
additional quiescent
supply current per
input pin
VI = VCC − 0.6 V;
IO = 0 A
2.7 to 3.6
−
−
5000
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2004 Mar 18
8
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to 85 °C; note 1
tPHL/tPLH propagation delay nCP to nQ and see Figs 6 and 8 1.2
−
15
−
ns
nCP to nQ
2.7
3.0 to 3.6
propagation delay nSD to nQ and see Figs 7 and 8 1.2
1.5
1.0
−
2.8
3.8(2)
16
7.3
6.8
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tW
nRD to nQ
2.7
1.5
1.0
−
4.0
3.2(2)
13
8.2
7.0
−
3.0 to 3.6
propagation delay nSD to nQ and see Figs 7 and 8 1.2
nRD to nQ
2.7
3.0 to 3.6
1.5
1.0
3.3
3.0
4.7
3.5(2)
2.0
−
7.1
6.5
−
clock pulse width HIGH or LOW
see Fig. 6
see Fig. 7
3.0 to 3.6
3.0 to 3.6
set or reset pulse width HIGH or
LOW
−
trem
tsu
removal time nSD, nRD to nCP
set-up time nJ and nK to CP
hold time nJ and nK to nCP
maximum clock pulse frequency
skew
see Fig. 7
see Fig. 6
see Fig. 6
see Fig. 6
note 3
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0
2.5
2.0
150
−
−
−
ns
−
−
ns
th
−
−
ns
fmax
tsk(0)
330
−
−
MHz
ns
1.0
2004 Mar 18
9
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
TEST CONDITIONS
WAVEFORMS CC (V)
SYMBOL
amb = −40 to 125 °C
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
T
tPHL/tPLH propagation delay nCP to nQ and see Figs 6 and 8 2.7
nCP to nQ
1.5
−
−
−
−
−
−
−
−
9.5
ns
3.0 to 3.6
1.0
1.5
1.0
1.5
1.0
3.3
3.0
8.5
10.5
9.0
9.0
8.5
−
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tW
propagation delay nSD to nQ and see Figs 7 and 8 2.7
nRD to nQ
3.0 to 3.6
propagation delay nSD to nQ and see Figs 7 and 8 2.7
nRD to nQ
3.0 to 3.6
clock pulse width HIGH or LOW
see Fig. 6
see Fig. 7
3.0 to 3.6
3.0 to 3.6
set or reset pulse width HIGH or
LOW
−
trem
tsu
removal time nSD, nRD to nCP
set-up time nJ and nK to CP
hold time nJ and nK to nCP
maximum clock pulse frequency
skew
see Fig. 7
see Fig. 6
see Fig. 6
see Fig. 6
note 3
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0
2.5
2.0
150
−
−
−
−
−
−
−
ns
−
ns
th
−
ns
fmax
tsk(0)
−
MHz
ns
1.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 Mar 18
10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
AC WAVEFORMS
V
I
V
nJ, nK input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
V
nCP input
M
GND
t
W
t
t
PLH
PHL
V
OH
V
nQ output
nQ output
M
V
OL
V
OH
V
M
V
OL
t
t
PHL
PLH
MNA860
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.6 Clock input (nCP) to output (nQ and nQ) propagation delays, the clock pulse width, the nJ and nK to nCP
set-up, the nCP to nJ and nK hold times and the maximum clock pulse frequency.
2004 Mar 18
11
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
V
I
V
nCP input
M
GND
t
rem
V
I
V
nSD input
nRD input
M
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
nQ output
nQ output
V
V
M
V
OL
V
OH
M
t
V
OL
MNA861
t
PHL
PLH
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Set (nSD) and reset (nRD) input to output (nQ and nQ) propagation delays, the set and reset pulse widths
and the nRD and nSD to nCP removal time.
2004 Mar 18
12
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
tPLH/tPHL
open
VCC
VI
CL
RL
1.2 V
2.7 V
VCC
50 pF
50 pF
50 pF
500 Ω(1)
500 Ω
2.7 V
2.7 V
open
open
3.0 to 3.6 V
500 Ω
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2004 Mar 18
13
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
2004 Mar 18
14
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
2004 Mar 18
15
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
2004 Mar 18
16
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74LVC109
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 18
17
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/04/pp18
Date of release: 2004 Mar 18
Document order number: 9397 750 10498
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