74LVC109DB,118_技术文档

74LVC109

Dual JK flip-flop with set and reset; positive-edge trigger

Rev. 5 — 29 November 2012

Product data sheet

1. General description

The 74LVC109A is a dual positive edge triggered JK flip-flop featuring:

• individual J and K inputs

• clock (CP) inputs

• set (SD) and reset (RD) inputs

• complementary Q and Q outputs

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input.

The J and K inputs control the state changes of the flip-flops as described in the mode

select function table. The J and K inputs must be stable one set-up time before the

LOW-to-HIGH clock transition for predictable operation. The JK design allows operation

as a D-type flip-flop by tying the J and K inputs together.

Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock

rise and fall times.

2. Features and benefits

 5 V tolerant inputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

3. Ordering information

Table 1.

Ordering information

All types are specified from 40  C to +125 C.

Type number

Package

Name

Description

Version

74LVC109D

74LVC109DB

74LVC109PW

SO16

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 5.3 mm

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT109-1

SOT338-1

SOT403-1

SSOP16

TSSOP16

4. Functional diagram

5

11

1SD 2SD

SD

5

2

11

14

S

1Q

2Q

6

2

14

4

1J

2J

1CP

2CP

J

Q

10

1J

6

7

10

9

CP

4

3

1

12

13

15

12

C1

FF

1Q

2Q

7

9

3

13

1K

2K

Q

K

1K

R

1K

R

RD

1RD 2RD

1 15

(a)

(b)

mna858

mna856

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Q

C

K

J

S

R

mna859

C

CP

Fig 3. Logic diagram for one flip-flop

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

2 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

5. Pinning information

5.1 Pinning

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1RD

1J

V

CC

2RD

2J

1K

1CP

1SD

1Q

2K

109

2CP

2SD

2Q

1Q

GND

2Q

001aad064

Fig 4. Pin configuration SO16 and (T)SSOP16

5.2 Pin description

Table 2.

Symbol

1RD

1J

Pin description

1

Description

asynchronous reset input (active LOW)

synchronous input

2

1K

3

synchronous input

1CP

1SD

1Q

4

clock input (LOW-to-HIGH; edge-triggered)

asynchronous set input (active LOW)

true flip-flop output

5

6

1Q

7

complement flip-flop output

ground (0 V)

GND

2Q

8

9

complement flip-flop output

true flip-flop output

2Q

10

11

12

13

14

15

16

2SD

2CP

2K

asynchronous set input (active LOW)

clock input (LOW-to-HIGH; edge-triggered)

synchronous input

2J

synchronous input

2RD

V_CC

asynchronous reset input (active LOW)

supply voltage

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

3 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

6. Functional description

Table 3.

Function selection^[1]

Operating modes

Input

nSD

L

Output

nRD

H

nCP

X

nJ

X

h

l

nK

X

l

nQ

H

L

nQ

L

Asynchronous set

Asynchronous reset

Undetermined

Toggle

H

L

X

H

q

L

X

H

q

H



Load 0 (reset)

Load 1 (set)

H



l

L

H

L

H



h

l

h

H

q

Hold no change

H



h

q

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition

L = LOW voltage level

l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition

q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition

X = don’t care

 = LOW-to-HIGH CP transition

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

[2]

V_I

+6.5

50

V_CC+ 0.5

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

V_O= 0 V to V_CC

mA

V

V_O

0.5

-

I_O

output current

mA

mW

C

I_CC

supply current

-

I_GND

P_tot

T_stg

ground current

100

-

[3]

total power dissipation

storage temperature

T_amb= 40 C to +125 C

500

+150

65

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO16 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

4 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

+125

20

V

V_O

output voltage

0

V

T_amb

t/V

ambient temperature

input transition rise and fall rate

in free air

40

0

C

ns/V

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

Min Max

Typ^[1]

1.08

40 C to +125 C

Min Max

1.08

Unit

V_IH

HIGH-level

V_CC= 1.2 V

-

V

input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65  V_CC

-

0.65  V_CC

1.7

-

1.7

V_CC= 2.7 V to 3.6 V

2.0

-

2.0

V_IL

LOW-level

V_CC= 1.2 V

-

0.12

-

0.12

input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

voltage

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

-

0.55

5

0.8

V

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

0.1

20

A

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

5 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Min Max

Unit

Min

Typ^[1]

Max

I_CC

supply

current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

10

-

40

A

I_CC

additional

supply

current

per input pin;

5

500

5000

-

V_CC= 2.7 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation nCP to nQ, nQ; see Figure 5

delay

V_CC= 1.2 V

-

15

6.8

3.9

3.5

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.7

2.7

1.5

1.0

15.0

8.1

7.3

6.8

1.7

2.7

1.5

1.0

17.4

9.4

9.5

8.5

V_CC= 3.0 V to 3.6 V

nSD, nRD to nQ, nQ; see Figure 6

V_CC= 1.2 V

t_PLH

LOW to

HIGH

propagation

delay

-

16

6.2

3.6

4.5

3.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

1.5

1.0

15.6

8.3

8.2

7.0

1.0

1.5

1.0

18.0

9.7

10.5

9.0

V_CC= 3.0 V to 3.6 V

nSD, nRD to nQ, nQ; see Figure 6

V_CC= 1.2 V

t_PHL

HIGH to

LOW

propagation

delay

-

13

6.7

3.8

4.1

3.5

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

2.0

1.5

1.0

14.4

7.7

7.1

6.5

1.5

2.0

1.5

1.0

16.7

9.0

8.5

V_CC= 3.0 V to 3.6 V

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

6 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

t_W

pulse width clock HIGH or LOW; see Figure 5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

5.0

4.0

3.3

-

5.0

4.0

3.3

-

ns

-

V_CC= 3.0 V to 3.6 V

set or reset HIGH or LOW; see Figure 6

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

5.0

4.0

3.0

-

5.0

4.0

3.0

-

ns

V_CC= 3.0 V to 3.6 V

nSD, nRD to nCP; see Figure 6

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_rec

recovery

time

5.5

4.0

3.2

3.0

-

5.5

4.0

3.2

3.0

-

ns

V_CC= 3.0 V to 3.6 V

t_su

set-up time nJ and nK to CP; see Figure 5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

5.0

3.5

2.7

2.5

-

5.0

3.5

2.7

2.5

-

ns

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

t_h

hold time

nJ and nK to nCP; see Figure 5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

3.0

2.5

2.2

2.0

-

3.0

2.5

2.2

2.0

-

ns

V_CC= 3.0 V to 3.6 V

see Figure 5

f_max

maximum

frequency

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

100

125

150

-

80

100

120

-

MHz

ns

-

330

-

V_CC= 3.0 V to 3.6 V

-

[3]

[4]

t_sk(o)

C_PD

output skew V_CC= 3.0 V to 3.6 V

time

1.0

1.5

power

V_I= GND to V_CC

dissipation

capacitance

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

-

11.4

17.6

23.1

-

pF

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] _pdis the same as t_PLHand t_PHL

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

t

.

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

7 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

[4] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

11. AC waveforms

V

I

V

nJ, nK input

GND

M

t

h

t

su

1/f

max

V

I

V

nCP input

M

GND

t

W

t

PLH

PHL

V

OH

V

nQ output

M

V

OL

V

OH

V

M

V

OL

t

PHL

PLH

mna860

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 5. Clock propagation delays, pulse width, set-up, hold times, and maximum frequency

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

8 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

V

I

V

M

nCP input

GND

t

rem

V

I

V

M

nSD input

nRD input

GND

t

W

V

I

V

M

GND

t

PHL

PLH

V

OH

nQ output

V

M

V

OL

V

OH

M

V

OL

t

PLH

PHL

mna861

Measurement points are given in Table 8.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 6. Set and reset propagation delays, pulse widths and recovery times

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

1.2 V

V_CC

2.7 V

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

9 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

O

I

PULSE

GENERATOR

DUT

R

T

C

L

R

L

001aaf615

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

Fig 7. Load circuitry for switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

t_r, t_f

R_L

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

10 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 8. Package outline SOT109-1 (SO16)

74LVC109

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Product data sheet

Rev. 5 — 29 November 2012

11 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig 9. Package outline SOT338-1 (SSOP16)

74LVC109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 29 November 2012

12 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 10. Package outline SOT403-1 (TSSOP16)

74LVC109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 29 November 2012

13 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20121129

Data sheet status

Change notice

Supersedes

74LVC109 v.5

Product data sheet

-

74LVC109 v.4

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVC109 v.4

74LVC109 v.3

74LVC109 v.2

74LVC109 v.1

20040318

19980428

19970318

-

Product specification

-

74LVC109 v.3

74LVC109 v.2

74LVC109 v.1

-

74LVC109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 29 November 2012

14 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74LVC109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 29 November 2012

15 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 29 November 2012

16 of 17

74LVC109

NXP Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 16

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 November 2012

Document identifier: 74LVC109


型号：	74LVC109DB,118
厂家：	NXP
描述：	74LVC109 - Dual JK(not) flip-flop with set and reset; positive-edge trigger SSOP1 16-Pin 光电二极管逻辑集成电路触发器
文件：	总17页 (文件大小：139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC109DB,118 [NXP]

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