74LVC10APW [NXP]
Triple 3-input NAND gate; 三路3输入与非门
| 型号： | 74LVC10APW |
| 厂家： | 
NXP |
| 描述： | Triple 3-input NAND gate |
| 文件： | 总8页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC10A
Triple 3-input NAND gate
Product specification
1998 Apr 28
Philips
Semiconductors
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
FEATURES
DESCRIPTION
The 74LVC10A is a high performance, low power, low voltage, Si
gate CMOS device and superior to most advanced CMOS
compatible TTL families.
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with JEDEC standard no. 8-1A.
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
The 74LVC10A provides the 3-input NAND function.
• I category: SSI
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
/t
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
nA, nB, nC to nY
C = 50 pF;
L
CC
t
3.9
ns
PHL PLH
V
= 3.3 V
C
Input capacitance
5.0
26
pF
pF
I
1
C
Power dissipation capacitance per gate
V = GND to V
I CC
PD
NOTE:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )ȍ (C × V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C × V
× f ) = sum of the outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVC10A D
DWG NUMBER
SOT108-1
14-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC10A D
74LVC10A DB
74LVC10A PW
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
74LVC10A DB
SOT337-1
74LVC10APW DH
SOT402-1
PIN CONFIGURATION
LOGIC SYMBOL
V
1A
1B
1
2
3
4
5
6
7
14
1
2
1A
1B
CC
1Y 12
13 1C
13 1C
2A
12 1Y
11 3C
10 3B
3
4
5
2A
2B
2C
2B
2Y
3Y
6
8
2C
2Y
9
8
3A
3Y
9
3A
10 3B
11 3C
GND
SV00416
SV00417
PIN DESCRIPTION
PIN
SYMBOL
NUMBER
NAME AND FUNCTION
1, 3, 9
2, 4, 10
7
1A – 3A
1B – 3B
GND
Data inputs
Data inputs
Ground (0 V)
Data outputs
12, 6, 8
13, 5, 11
14
1Y – 3Y
1C – 3C
Data inputs
V
CC
Positive supply voltage
2
1998 Apr 28
853-1973 19308
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
LOGIC SYMBOL (IEEE/IEC)
FUNCTION TABLE
INPUTS
OUTPUTS
nY
1
2
13
&
12
nA
nB
nC
3
4
5
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
&
6
9
10
11
&
8
H
H
H
H
H
L
L
H
H
L
H
L
H
H
H
L
SV00418
H
LOGIC DIAGRAM (ONE GATE)
NOTES:
H = HIGH voltage level
L = LOW voltage level
A
B
C
Y
SV00419
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
3.6
V
V
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
V
V
CC
3.6
5.5
CC
V
I
V
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +6.5
–50
UNIT
V
V
CC
I
IK
DC input diode current
V t 0
mA
V
I
V
I
DC input voltage
Note 2
–0.5 to +6.5
"50
I
DC output diode current
DC output voltage; output HIGH or LOW
V
O
uV or V t 0
mA
OK
CC
O
Note 2
Note 2
–0.5 to V +0.5
CC
V
I/O
V
DC input voltage; output 3-State
DC output source or sink current
–0.5 to 6.5
I
O
V
O
= 0 to V
"50
"100
mA
mA
°C
CC
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3
1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*1.0
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
V
= 3.0V; V = V or V I
= –12mA
I = –24mA
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
10
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
V
OL
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND
"0.1
µA
µA
I
I
I
Quiescent supply current
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF
r
f
L
LIMITS
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
SYMBOL
PARAMETER
WAVEFORM
UNIT
1
MIN
1.5
TYP
MAX
MIN
MAX
t
t
/
Propagation delay
nA, nB, nC to nY
PHL
Figures 1, 2
3.9
5.7
1.5
6.7
ns
PLH
NOTE:
1. These typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC WAVEFORMS
TEST CIRCUIT
V
V
V
= 1.5 V at V w 2.7 V
M
CC
S
1
= 0.5 S V at V < 2.7 V
M
CC
CC
2 * V
V
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
Open
GND
output load.
500Ω
V
V
O
I
V
I
PULSE
GENERATOR
D.U.T.
nA, nB, nC
INPUT
GND
V
M
50pF
500Ω
R
T
C
L
t
t
PLH
PHL
V
OH
nY OUTPUT
V
V
M
SWITCH POSITION
TEST
S
V
V
I
OL
1
CC
SV00420
t
t
Open
< 2.7V
V
CC
PLH/ PHL
Figure 1. Input (nA, nB, nC) to output (nY)
propagation delays.
2.7–3.6V
2.7V
SV00903
Figure 2. Load circuitry for switching times.
4
1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
5
1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
6
1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
7
1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 07-98
9397-750-04482
Document order number:
Philips
Semiconductors
相关型号：
74LVC10APW-T
IC LVC/LCX/Z SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
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