74LVC11PW,112 [NXP]
74LVC11 - Triple 3-input AND gate TSSOP 14-Pin;
| 型号： | 74LVC11PW,112 |
| 厂家： | 
NXP |
| 描述： | 74LVC11 - Triple 3-input AND gate TSSOP 14-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC11
Triple 3-input AND gate
Product specification
2004 Jan 13
Supersedes data of 1998 Apr 28
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
FEATURES
DESCRIPTION
• Wide supply voltage range from1.2 to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
The 74LVC11 is a high-performance, low power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC11 provides the 3-input AND function.
• ICC category: SSI
• In accordance with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
CI
PARAMETER
propagation delay nA, nB, nC to nY
input capacitance
CONDITIONS
TYPICAL
3.7
UNIT
CL = 50 pF; VCC = 3.3 V
ns
pF
pF
5.0
26
CPD
power dissipation capacitance per gate notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74LVC11D
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
14
14
14
14
SO14
plastic
plastic
plastic
plastic
SOT108-1
SOT337-1
SOT402-1
SOT762-1
74LVC11DB
74LVC11PW
74LVC11BQ
SSOP14
TSSOP14
DHVQFN14
2004 Jan 13
2
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
FUNCTION TABLE
See note 1.
INPUT
nB
OUTPUT
nY
nA
nC
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Note
1. H = HIGH voltage level.
L = LOW voltage level.
PINNING
PIN
1
SYMBOL
1A
DESCRIPTION
data input
data input
data input
data input
data input
2
1B
3
2A
4
2B
5
2C
2Y
6
data output
ground (0 V)
data output
data input
7
GND
3Y
8
9
3A
10
11
12
13
14
3B
data input
3C
1Y
data input
data output
data input
1C
VCC
positive supply voltage
2004 Jan 13
3
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
V
1A
1
handbook, halfpage
CC
14
handbook, halfpage
1A
1B
1
2
3
4
5
6
7
V
CC
14
13
12
11
10
9
1B
2
3
13 1C
12 1Y
1C
1Y
3C
3B
3A
3Y
2A
2A
(1)
2B
2C
2Y
4
5
6
11 3C
10 3B
GND
2B
11
2C
2Y
9
3A
8
GND
7
8
MNA791
GND 3Y
Top view
MNA970
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
1
handbook, halfpage
handbook, halfpage
&
&
&
12
6
1
2
1A
1B
1C
2A
2B
2C
3A
3B
3C
2
1Y
2Y
12
6
13
13
3
3
4
5
4
5
9
9
10
11
3Y
8
10
11
8
MNA793
MNA792
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Jan 13
4
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
handbook, halfpage
A
B
C
Y
MNA794
Fig.5 Logic diagram (one gate).
2004 Jan 13
5
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VCC
for maximum speed performance 2.7
V
V
V
V
for low-voltage applications
1.2
0
3.6
5.5
VCC
+85
20
VI
input voltage
VO
output voltage
0
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
output diode current
output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
VO
−0.5
−
VCC + 0.5
±50
IO
output source or sink current
VCC or GND current
storage temperature range
power dissipation
VO = 0 to VCC
mA
mA
°C
IGND, ICC
Tstg
Ptot
−
±100
+150
500
−65
−
Tamb = −40 to +125 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of PD derates linearly with 4.5 mW/K.
2004 Jan 13
6
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
DC CHARACTERISTICS
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH level input voltage
1.2
VCC
−
−
−
V
V
V
V
2.7 to 3.6
1.2
2.0
−
−
−
−
LOW-level input voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −12 mA
IO = −100 µA
IO = −12 mA
IO = −24 mA
2.7
3.0
3.0
3.0
V
V
V
V
CC − 0.5
−
−
−
−
−
V
V
V
V
CC − 0.2 VCC
CC − 0.6
CC − 1.0
−
−
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 12 mA
2.7
3.0
3.0
3.6
3.6
−
−
−
−
−
−
0.40
0.20
0.55
±5
V
V
V
IO = 100 µA
GND
−
IO = 24 mA
ILI
input leakage current
VI = 5.5 V or GND
±0.1
0.1
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
10
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin IO = 0
2.7 to 3.6
−
5
500
µA
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay
see Figs 6 and 7
2.7
3.0 to 3.6
−
−
−
7.0
6.2
ns
ns
3.7
Note
1. Typical value is measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Jan 13
7
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
AC WAVEFORMS
V
handbook, halfpage
I
V
nA, nB, nC input
M
GND
t
t
PLH
PHL
V
OH
V
nY output
M
MNA795
V
OL
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.6 Input (nA, nB and nC) to output (nY) propagation delays.
S1
2 × V
CC
open
GND
V
CC
R
R
= 500 Ω
= 500 Ω
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
=
L
R
L
T
50 pF
MNA815
SWITCH POSITION
TEST S1
tPLH/tPHL
VCC
<2.7 V
2.7 to 3.6 V
VI
VCC
2.7 V
open
Definitions for test circuit:
RL = load resistor.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
8
2004 Jan 13
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2004 Jan 13
9
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
2004 Jan 13
10
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2004 Jan 13
11
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2004 Jan 13
12
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Jan 13
13
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/04/pp14
Date of release: 2004 Jan 13
Document order number: 9397 750 10501
相关型号：
74LVC11PW-T
IC LVC/LCX/Z SERIES, TRIPLE 3-INPUT AND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, Gate
NXP
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