74LVC14APW118_技术文档

74LVC1G99

Ultra-conﬁgurable multiple function gate; 3-state

Rev. 01 — 3 January 2008

Product data sheet

1. General description

The 74LVC1G99 provides a low voltage, ultra-conﬁgurable, multiple function gate with

3-state output. The device can be conﬁgured as one of several logic functions including,

AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components

are required to conﬁgure the device as all inputs can be connected directly to V_CCor GND.

The 3-state output is controlled by the output enable input (OE). A HIGH level at OE

causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the

output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and

D).

Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input

signals, transforming them into sharply deﬁned, jitter free output signals. By eliminating

leakage current paths to V_CCand GND, the inputs and disabled output are also

over-voltage tolerant, making the device suitable for mixed-voltage applications.

This device is fully speciﬁed for partial power-down applications using I_OFF

.

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74LVC1G99 is fully speciﬁed over the supply range from 1.65 V to 5.5 V.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC1G99DP

74LVC1G99GT

74LVC1G99GM

−40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

XSON8

plastic extremely thin small outline package; no leads; SOT833-1

8 terminals; body 1 × 1.95 × 0.5 mm

XQFN8U plastic extremely thin quad ﬂat package; no leads;

SOT902-1

8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm

4. Marking

Table 2.

Marking

Type number

74LVC1G99DP

74LVC1G99GT

74LVC1G99GM

Marking code

V99

5. Functional diagram

OE

A

B

Y

C

D

001aah322

Fig 1. Logic symbol

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

2 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

6. Pinning information

6.1 Pinning

74LVC1G99

1

2

3

4

8

7

6

5

OE

A

V

Y

CC

B

D

C

GND

001aah323

Fig 2. Pin conﬁguration SOT505-2 (TSSOP8)

74LVC1G99

terminal 1

index area

74LVC1G99

Y

1

OE

A

1

2

3

4

8

7

6

5

V

Y

CC

7

6

5

OE

A

D

C

2

3

B

D

C

B

GND

001aah325

001aah324

Transparent top view

Fig 3. Pin conﬁguration SOT833-1 (XSON8)

Fig 4. Pin conﬁguration SOT902-1 (XQFN8U)

6.2 Pin description

Table 3.

Symbol

Pin description

Description

SOT505-2 and

SOT833-1

SOT902-1

OE

A

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

8

output enable input OE (active LOW)

data input

B

data input

GND

C

ground (0 V)

data input

D

data input

Y

data output

V_CC

supply voltage

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

3 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7. Functional description

Table 4.

Function table ^[1]

Input

OE

L

Output

D

L

C

L

B

L

A

L

Y

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

X

L

H

L

H

L

H

L

H

L

H

X

H

L

H

L

H

X

L

H

X

L

H

Z

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

Z = high-impedance OFF-state.

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

4 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7.1 Logic conﬁgurations

Table 5.

Function selection table

Primary function

Complementary function

3-state buffer

3-state inverter

3-state 2-input multiplexer

3-state 2-input multiplexer with inverting output

3-state 2-input AND

3-state 2-input NOR with two inverting inputs

3-state 2-input NOR with one inverting input

3-state 2-input NOR

3-state 2-input AND with one inverting input

3-state 2-input AND with two inverting inputs

3-state 2-input NAND

3-state 2-input OR with two inverting inputs

3-state 2-input OR with one inverting input

3-state 2-input OR

3-state 2-input NAND with one inverting input

3-state 2-input NAND with two inverting inputs

3-state 2-input XOR

3-state 2-input XNOR

3-state 2-input XOR with one inverting input

7.2 3-state buffer functions available

Table 6.

Function table ^[1]

See Figure 5.

Function

Input

OE

L

A

B

C

D

3-state buffer

input

H or L

L

H or L

input

H

L

H

input

L

H

L

H

L

H

H or L

input

L

H or L

L

H

L

H or L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input

Y

001aah326

Fig 5. 3-state buffer function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

5 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7.3 3-state inverter functions available

Table 7.

Function table ^[1]

See Figure 6.

Function

Input

OE

L

A

B

C

D

3-state inverter

input

H or L

input

H

L

H

L

X

H

L

input

L

H

L

H

L

H

H or L

H

input

L

H or L

H

L

H

H or L

[1] H = HIGH voltage level;

L = LOW voltage level.

X = don’t care.

OE

input

Y

001aah327

Fig 6. 3-state inverter function

7.4 3-state multiplexer functions available

Table 8.

Function table ^[1]

See Figure 7.

Function

Input

OE

L

A

B

C

D

L

3-state 2-input

multiplexer

input 1

input 2

input 1

input 2

input 1

input 2

input 1

input 1 or input 2

input 2 or input 1

input 1 or input 2

input 2 or input 1

L

H

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

Y

input 2

A/B

input 2

A/B

001aah328

Fig 7. 3-state 2-input multiplexer function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

6 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7.5 3-state AND/NOR functions available

Table 9.

Function table ^[1]

See Figure 8.

Number of inputs Function

AND/NAND

Input

OE

L

OR/NOR

A

L

B

C

D

L

2

3-state AND

3-state NOR

input 1

input 2

input 1

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah329

Fig 8. 3-state AND/NOR function

Table 10. Function table ^[1]

See Figure 9.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

L

2

3-state AND

3-state NOR

input 2

H

L

input 1

input 2

L

input 1

H

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah330

Fig 9. 3-state AND/NOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

7 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 11. Function table ^[1]

See Figure 10.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

L

2

3-state AND

3-state NOR

input 1

H

L

input 2

input 1

L

input 2

H

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah331

Fig 10. 3-state AND/NOR function

Table 12. Function table ^[1]

See Figure 11.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

L

2

3-state AND

3-state NOR

input 1

input 2

H

input 2

input 1

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah332

Fig 11. 3-state AND/NOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

8 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7.6 3-state NAND/OR functions available

Table 13. Function table ^[1]

See Figure 12.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

L

B

C

D

H

2

3-state NAND

3-state OR

input 1

input 2

input 1

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah333

Fig 12. 3-state NAND/OR function

Table 14. Function table ^[1]

See Figure 13.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

H

L

2

3-state NAND

3-state OR

input 2

H

L

input 1

input 2

L

input 1

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah334

Fig 13. 3-state AND/NOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

9 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 15. Function table ^[1]

See Figure 14.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

H

L

2

3-state NAND

3-state OR

input 1

H

L

input 2

input 1

L

input 2

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah335

Fig 14. 3-state AND/NOR function

Table 16. Function table ^[1]

See Figure 15.

Number of inputs Function

AND/NAND

Input

OR/NOR

OE

L

A

B

C

D

L

2

3-state NAND

3-state OR

input 1

input 2

H

input 2

input 1

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

OE

input 1

input 2

Y

001aah336

Fig 15. 3-state AND/NOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

10 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

7.7 3-state XOR/XNOR functions available

Table 17. Function table ^[1]

See Figure 16.

Function

Input

OE

L

A

B

C

D

3-state XOR

input 1

input 2

H or L

L

H or L

input 1

input 2

H

L

input 2

input 1

input 2

input 1

input 2

input 1

L

H

L

H

L

input 1

input 2

L

H

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

Y

001aah337

Fig 16. 3-state XOR function

Table 18. Function table ^[1]

See Figure 17.

Function

Input

OE

L

A

B

C

D

3-state XOR

H

L

input 1

input 2

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

Y

001aah338

Fig 17. 3-state XOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

11 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 19. Function table ^[1]

See Figure 18.

Function

Input

OE

L

A

B

C

D

3-state XOR

H

L

input 1

input 2

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

Y

001aah339

Fig 18. 3-state XOR function

Table 20. Function table ^[1]

See Figure 19.

Function

Input

OE

L

A

H

B

L

C

D

3-state XNOR

input 1

input 2

input 1

L

[1] H = HIGH voltage level;

L = LOW voltage level.

OE

input 1

input 2

Y

001aah340

Fig 19. 3-state XNOR function

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

12 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

8. Limiting values

Table 21. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

±50

V_CC+ 0.5

+6.5

±50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

Active mode

mA

V

[1][2]

V_O

−0.5

-

Power-down mode

V_O= 0 V to V_CC

V

I_O

output current

mA

mW

°C

I_CC

I_GND

P_tot

T_stg

supply current

-

ground current

−100

-

[3]

total power dissipation

storage temperature

T_amb= −40 °C to +125 °C

250

+150

−65

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When V_CC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP8 package: above 110 °C the value of P_totderates linearly with 8.0 mW/K.

For XSON8 and XQFN8U packages: above 45 °C the value of P_totderates linearly with 2.4 mW/K.

9. Recommended operating conditions

Table 22. Recommended operating conditions

Symbol

V_CC

V_I

Parameter

Conditions

Min

Typ

Max

5.5

V_CC

5.5

+125

20

Unit

V

supply voltage

input voltage

output voltage

1.65

-

0

V

V_O

Active mode

0

V

Power-down mode; V_CC= 0 V

0

V

T_amb

ambient temperature

−40

°C

∆t/∆V

input transition rise and fall rate V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 4.5 V

-

ns/V

10

V_CC= 4.5 V to 5.5 V

5

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

13 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

10. Static characteristics

Table 23. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

T_amb= −40 °C to +85 °C

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 µA; V_CC= 1.65 V to 5.5 V

V

_CC− 0.1

-

V

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

1.2

1.9

2.2

2.3

3.8

V_OL

LOW-level output voltage

I_O= 100 µA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

-

0.1

V

-

0.45

0.3

V

-

V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

V_CC= 0 V to 5.5 V; V_I= 5.5 V or GND

-

0.4

V

-

0.55

±5

V

-

V

I_I

input leakage current

±0.1

µA

I_OZ

OFF-state output current

V_CC= 3.6 V; V_I= V_IHor V_IL;

V_O= 5.5 V or GND

±10

I_OFF

I_CC

power-off leakage current V_CC= 0 V; V_Ior V_O= 5.5 V

-

±0.1

±10

µA

supply current

V_CC= 1.65 V to 5.5 V;

0.1

10

V_I= 5.5 V or GND; I_O= 0 A

∆I_CC

additional supply current

input capacitance

per pin; V_CC= 2.3 V to 5.5 V;

V_I= V_CC− 0.6 V; I_O= 0 A

-

5

500

-

µA

C_I

V_CC= 3.3 V; V_I= GND to V_CC

2.5

pF

T_amb= −40 °C to +125 °C

V_OHHIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 µA; V_CC= 1.65 V to 5.5 V

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

V

_CC− 0.1

-

V

0.95

1.7

1.9

2.0

3.4

V_OL

LOW-level output voltage

I_O= 100 µA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

-

0.1

V

0.70

0.45

0.60

0.80

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

14 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 23. Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

µA

I_I

input leakage current

OFF-state output current

V_CC= 0 V to 5.5 V; V_I= 5.5 V or GND

-

±100

±200

I_OZ

V_CC= 3.6 V; V_I= V_IHor V_IL;

V_O= 5.5 V or GND

µA

I_OFF

I_CC

power-off leakage current V_CC= 0 V; V_Ior V_O= 5.5 V

-

±200

µA

supply current

V_CC= 1.65 V to 5.5 V;

200

V_I= 5.5 V or GND; I_O= 0 A

∆I_CC

additional supply current

per pin; V_CC= 2.3 V to 5.5 V;

-

5000

µA

V_I= V_CC− 0.6 V; I_O= 0 A

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

11. Dynamic characteristics

Table 24. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22.

Symbol Parameter

Conditions

25 °C

Min Typ^[1]Max

−40 °C to +125 °C

Unit

Min

Max

(85 °C) (125 °C)

[2]

t_pd

propagation delay A to Y; see Figure 20

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

-

7.5

5.0

5.4

4.5

3.8

-

2.8

2.0

1.8

30.8

11.7

9.0

38.5

14.6

11.3

10.5

6.9

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

B to Y; see Figure 20

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

8.4

5.5

-

7.5

5.0

5.4

4.5

3.8

-

2.8

2.0

1.8

28.9

11.3

9.0

36.2

14.2

11.3

10.3

6.8

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

C to Y; see Figure 20

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

8.2

5.4

-

7.8

5.2

5.3

4.6

3.8

-

3.2

2.3

1.8

29.8

12.3

9.6

37.3

15.4

12.0

10.8

7.2

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

D to Y; see Figure 20

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

8.6

5.7

-

7.0

4.6

4.8

4.1

3.4

-

2.8

2.0

1.8

1.6

25.7

10.7

9.2

32.2

13.4

11.5

9.5

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

7.6

5.2

6.5

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

15 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 24. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ^[1]Max

Min

Max

(85 °C) (125 °C)

[3]

[4]

[5]

t_en

enable time

OE to Y; see Figure 21

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

-

5.7

3.8

4.2

3.5

2.7

-

2.0

1.4

25.2

11.3

8.6

32.0

14.0

11.0

9.0

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

OE to Y; see Figure 21

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

7.0

4.7

6.0

t_dis

disable time

-

5.7

3.6

4.5

3.4

-

3.0

2.0

2.1

1.0

15.0

5.8

6.6

5.9

4.5

19.0

7.3

8.2

7.4

5.6

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

C_PD

power dissipation per buffer (output enabled);

capacitance

f_i= 10 MHz; C_L= 50 pF;

V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

-

14

16

18

25

30

-

pF

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] t_enis the same as t_PZHand t_PZL

[4] t_disis the same as t_PHZand t_PLZ

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

16 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

12. Waveforms

V

I

V

M

A, B, C, D input

GND

M

t

PLH

PHL

V

OH

V

Y output

M

V

OL

t

PHL

PLH

V

OH

Y output

M

V

OL

001aah341

Measurement points are given in Table 25.

Logic levels: V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig 20. The data input (A, B, C, D) to output (Y) propagation delays

V

I

OE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna644

Measurement points are given in Table 25.

Logic levels: V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig 21. 3-state enable and disable times

Table 25. Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

V_X

V_Y

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

0.5V_CC

1.5 V

0.5V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V

_OH− 0.15 V

_OH− 0.3 V

3.0 V to 3.6 V

4.5 V to 5.5 V

1.5 V

0.5V_CC

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

17 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

L

mna616

Test data is given in Table 26.

Deﬁnitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 22. Load circuitry for switching times

Table 26. Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r= t_f

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

2V_CC

6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

V_CC

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

open

GND

open

GND

3.0 V to 3.6 V

4.5 V to 5.5 V

open

GND

6 V

open

GND

2V_CC

13. Transfer characteristics

Table 27. Transfer characteristics

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22

Symbol Parameter

Conditions

−40 °C to +85 °C

Min Max

Typ^[1]

−40 °C to +125 °C

Min Max

Unit

V_T+

positive-going

see Figure 23, Figure 24,

threshold voltage Figure 25, Figure 26 and

Figure 27

V_CC= 1.8 V

V_CC= 2.3 V

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 5.5 V

0.70

1.11

1.50

2.16

2.61

1.02

1.20

1.60

2.00

2.74

3.33

0.67

1.20

V

1.42

1.79

2.52

2.99

1.08

1.47

2.13

2.58

1.60

2.00

2.74

3.33

V

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

18 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

Table 27. Transfer characteristics …continued

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22

Symbol Parameter

Conditions

−40 °C to +85 °C

Min Max

Typ^[1]

−40 °C to +125 °C

Min Max

Unit

V_T−

negative-going

see Figure 23, Figure 24,

threshold voltage Figure 25, Figure 26 and

Figure 27

V_CC= 1.8 V

V_CC= 2.3 V

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 5.5 V

0.30

0.58

0.80

1.21

1.45

0.53

0.72

1.00

1.30

1.90

2.29

0.30

0.75

V

0.77

1.04

1.55

1.86

0.58

0.80

1.21

1.45

1.03

1.33

1.93

2.32

V

V_H

hysteresis voltage (V_T+− V_T−); see Figure 23,

Figure 24, Figure 25,

Figure 26 and Figure 27

V_CC= 1.8 V

V_CC= 2.3 V

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 5.5 V

0.30

0.40

0.50

0.71

0.48

0.64

0.75

0.97

1.13

0.62

0.80

1.00

1.20

1.40

0.23

0.34

0.44

0.65

0.62

0.80

1.00

1.20

1.40

V

[1] All typical values are measured at T_amb= 25 °C

14. Waveforms transfer characteristics

V

O

V

T+

V

I

V

H

V

T−

V

I

V

O

H

V

T+

T−

mna207

mna208

Fig 23. Transfer characteristic

Fig 24. Deﬁnition of V_T+, V_T−and V_H

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

19 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

V

O

V

T+

V

I

V

H

V

T−

V

O

V

I

V

H

V

T+

T−

mnb155

mnb154

Fig 25. Transfer characteristic

Fig 26. Deﬁnition of V_T+, V_T−and V_H

001aab594

16

I

CC

(mA)

12

8

4

0

1

2

3

V (V)

I

Fig 27. Typical 74LVC1G99 transfer characteristic; V_CC= 3.0 V

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

20 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

15. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A

X

c

H

v

M

y

A

E

Z

5

8

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

mm

1.1

0.65

0.25

0.5

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig 28. Package outline SOT505-2 (TSSOP8)

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

21 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

b

1

2

3

4

4×

(2)

L

1

e

8

7

6

5

e

1

e

1

e

1

8×

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

1

L

1

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

07-11-14

07-12-07

SOT833-1

- - -

MO-252

Fig 29. Package outline SOT833-1 (XSON8)

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

22 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

XQFN8U: plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm

SOT902-1

D

B

A

terminal 1

index area

E

A

1

detail X

e

L

1

e

C

y

C

1

y

L

M

v

C A

C

B

4

w

5

6

7

3

2

metal area

not for soldering

e

1

b

e

1

terminal 1

index area

8

X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

b

D

E

e

1

L

v

w

y

1

max

0.05 0.25 1.65 1.65

0.00 0.15 1.55 1.55

0.35 0.15

0.25 0.05

mm

0.5

0.55

0.5

0.1

0.05 0.05 0.05

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

MO-255

JEITA

05-11-25

07-11-14

SOT902-1

- - -

Fig 30. Package outline SOT902-1 (XQFN8U)

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

23 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

16. Abbreviations

Table 28. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

17. Revision history

Table 29. Revision history

Document ID

Release date

20080103

Data sheet status

Change notice

Supersedes

74LVC1G99_1

Product data sheet

-

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

24 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

18.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

19. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

74LVC1G99_1

Product data sheet

Rev. 01 — 3 January 2008

25 of 26

74LVC1G99

NXP Semiconductors

Ultra-conﬁgurable multiple function gate; 3-state

20. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 4

Logic conﬁgurations . . . . . . . . . . . . . . . . . . . . . 5

3-state buffer functions available . . . . . . . . . . . 5

3-state inverter functions available . . . . . . . . . . 6

3-state multiplexer functions available . . . . . . . 6

3-state AND/NOR functions available. . . . . . . . 7

3-state NAND/OR functions available. . . . . . . . 9

3-state XOR/XNOR functions available . . . . . 11

7.1

7.2

7.3

7.4

7.5

7.6

7.7

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

Recommended operating conditions. . . . . . . 13

Static characteristics. . . . . . . . . . . . . . . . . . . . 14

Dynamic characteristics . . . . . . . . . . . . . . . . . 15

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transfer characteristics. . . . . . . . . . . . . . . . . . 18

Waveforms transfer characteristics. . . . . . . . 19

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

9

10

11

12

13

14

15

16

17

18

Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18.1

18.2

18.3

18.4

19

20

Contact information. . . . . . . . . . . . . . . . . . . . . 25

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 January 2008

Document identifier: 74LVC1G99_1


型号：	74LVC14APW118
厂家：	NXP
描述：	Hex inverting Schmitt trigger with 5 V tolerant input 六角反相施密特触发器具有5 V容限输入触发器
文件：	总26页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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