74LVC157AD,112 [NXP]
74LVC157A - Quad 2-input multiplexer SOP 16-Pin;
| 型号： | 74LVC157AD,112 |
| 厂家： | 
NXP |
| 描述： | 74LVC157A - Quad 2-input multiplexer SOP 16-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC157A
Quad 2-input multiplexer
Product specification
2003 Dec 02
Supersedes data of 2003 Jun 17
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
FEATURES
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74LVC157A is a quad 2-input multiplexer which select
four bits of data from two sources under the control of a
common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable
input (E) is active LOW. When pin E is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all the
other input conditions. Moving the data from two groups of
registers to four common output buses is a common use of
the 74LVC157A. The state of the common data select
input (S) determines the particular register from which the
data comes. It can also be used as function generator.
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
The device is useful for implementing highly irregular logic
by generating any 4 of the 16 different functions of two
variables with one variable common.
DESCRIPTION
The 74LVC157A is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC157A is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to pin S.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
propagation delay
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
nI0, nI1 to nY
E to nY
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
2.6
ns
ns
ns
pF
pF
2.8
2.6
5.0
15
S to nY
CI
input capacitance
CPD
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2003 Dec 02
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nY
E
S
nI0
nI1
H
L
L
L
L
X
L
X
L
X
X
X
L
L
L
L
H
X
X
H
L
H
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
PACKAGE
TEMPERATURE
RANGE
TYPE NUMBER
PINS
PACKAGE
MATERIAL
plastic
CODE
74LVC157AD
74LVC157ADB
74LVC157APW
74LVC157ABQ
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
16
16
16
16
SO16
SOT109-1
SOT338-1
SOT403-1
SOT763-1
SSOP16
plastic
TSSOP16
DHVQFN16
plastic
plastic
PINNING
PIN
1
SYMBOL
DESCRIPTION
S
common data select input
data input from source 0
data input from source 1
multiplexer output
2
1I0
1I1
1Y
3
4
5
2I0
2I1
2Y
data input from source 0
data input from source 1
multiplexer output
6
7
8
GND
3Y
ground (0 V)
9
multiplexer output
10
11
12
13
14
15
16
3I1
3I0
4Y
data input from source 1
data input from source 0
multiplexer output
4I1
4I0
E
data input from source 1
data input from source 0
enable input (active LOW)
supply voltage
VCC
2003 Dec 02
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
V
S
1
handbook, halfpage
CC
16
handbook, halfpage
1I0
2
3
15
E
V
E
1
2
3
4
5
6
7
8
16
15
S
1I0
1I1
1Y
CC
1I1
14 4I0
14 4I0
1Y
2I0
2I1
2Y
4
5
6
7
13 4I1
12 4Y
11 3I0
10 3I1
(1)
13
12
11
10
9
GND
4I1
4Y
157
2I0
2I1
3I0
3I1
3Y
2Y
GND
8
GND
9
MNA480
3Y
Top view
MDB106
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
handbook, halfpage
1
G1
15
EN
2
3
5
6
11 10 14 13
handbook, halfpage
2
1
1
MUX
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
4
7
9
3
5
6
1
S
E
15
1Y
4
2Y
7
3Y
9
4Y
12
11
10
MNA481
14
13
12
MNA482
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2003 Dec 02
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
handbook, halfpage
1I0
1I1
2
3
1Y
2Y
3Y
4Y
4
7
2I0
2I1
3I0
3I1
4I0
5
6
MULTIPLEXER
OUTPUTS
SELECTOR
11
10
14
9
12
13 4I1
S
1
E
MNA483
15
Fig.5 Functional diagram.
handbook, halfpage
S
E
1I1
1Y
2Y
3Y
4Y
1I0
2I1
2I0
3I1
3I0
4I1
4I0
MNA484
Fig.6 Logic diagram.
5
2003 Dec 02
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VCC
for maximum speed performance 2.7
V
for low voltage applications
1.2
3.6
5.5
VCC
+125
20
V
VI
input voltage
0
V
VO
output voltage
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
VO
IO
output diode current
output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
−0.5
−
VCC + 0.5
±50
output source or sink current
VO = 0 to VCC
mA
mA
°C
ICC, IGND VCC or GND current
−
±100
+150
500
Tstg
PD
storage temperature
power dissipation
−65
−
Tamb = −40 to +125 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO16 packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of PD derates linearly with 4.5 mW/K.
2003 Dec 02
6
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input
voltage
1.2
VCC
−
−
−
−
−
−
V
V
V
V
2.7 to 3.6
1.2
2.0
−
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.2
−
−
−
−
−
−
−
−
V
V
V
V
CC − 0.5
CC − 0.6
CC − 0.8
3.0
3.0
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
−
−
−
0.2
0.4
0.55
±5
V
V
V
IO = 12 mA
IO = 24 mA
3.0
ILI
input leakage
current
VI = 5.5 V or GND
3.6
±0.1
0.1
5
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
3.6
−
−
10
additional quiescent VI =VCC − 0.6 V;
2.7 to 3.6
500
supply current per
input pin
IO = 0
2003 Dec 02
7
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH
HIGH-level input
voltage
1.2
VCC
−
−
−
−
−
−
V
V
V
V
2.7 to 3.6
1.2
2.0
−
VIL
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.3
−
−
−
−
−
−
−
−
V
V
V
V
CC − 0.65
CC − 0.75
CC − 1
3.0
3.0
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
−
−
−
−
0.3
0.6
0.8
±20
V
V
V
IO = 12 mA
IO = 24 mA
3.0
ILI
input leakage
current
VI = 5.5 V or GND
3.6
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
3.6
−
−
−
−
40
additional quiescent VI =VCC − 0.6 V;
2.7 to 3.6
5000
supply current per
input pin
IO = 0
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Dec 02
8
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +85 °C; note 1
tPHL/tPLH
propagation delay nI0,
nI1 to nY
see Figs 8 and 9 1.2
2.7
−
16
−
ns
1.0
1.0
−
3.0
2.6(2)
5.9
5.2
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0 to 3.6
propagation delay E to nY
propagation delay S to nY
skew
see Figs 7 and 9 1.2
2.7
17
1.0
1.0
−
3.4
2.8(2)
7.8
6.5
−
3.0 to 3.6
see Figs 8 and 9 1.2
2.7
16
1.0
1.0
−
3.0
2.6(2)
7.3
6.3
1.0
3.0 to 3.6
3.0 to 3.6
tsk(0)
note 3
−
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay nI0,
nI1 to nY
see Figs 8 and 9 1.2
2.7
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
−
7.5
6.5
−
3.0 to 3.6
propagation delay E to nY
see Figs 7 and 9 1.2
2.7
1.0
1.0
−
10.0
8.5
−
3.0 to 3.6
propagation delay S to nY
skew
see Figs 8 and 9 1.2
2.7
1.0
1.0
−
9.5
8.0
1.5
3.0 to 3.6
3.0 to 3.6
tsk(0)
note 3
Notes
1. All typical values are measured at Tamb = 25 °C.
2. This typical value is measured at VCC = 3.3 V and Tamb = 25 °C.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2003 Dec 02
9
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
AC WAVEFORMS
V
handbook, halfpage
CC
V
E input
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
MNA485
OL
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
1.2 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Enable input (E) to output (nY) propagation delays.
V
handbook, halfpage
nI0, nI1, S
input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
MNA486
OL
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
1.2 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.8 Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays.
2003 Dec 02
10
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
S1
2 × V
open
GND
CC
V
CC
R
L
500 Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
R
L
L
R
T
500 Ω
MNA368
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.2 V
2.7 V
50 pF
50 pF
50 pF
500 Ω(1) open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
500 Ω
500 Ω
open
open
3.0 to 3.6 V
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuitry for switching times.
2003 Dec 02
11
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
2003 Dec 02
12
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
2003 Dec 02
13
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
2003 Dec 02
14
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
2003 Dec 02
15
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Dec 02
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/05/pp17
Date of release: 2003 Dec 02
Document order number: 9397 750 12371
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