74LVC157APW-Q100J [NXP]

74LVC157A-Q100 - Quad 2-input multiplexer TSSOP 16-Pin;
74LVC157APW-Q100J
型号: 74LVC157APW-Q100J
厂家: NXP    NXP
描述:

74LVC157A-Q100 - Quad 2-input multiplexer TSSOP 16-Pin

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74LVC157A-Q100  
Quad 2-input multiplexer  
Rev. 2 — 2 May 2013  
Product data sheet  
1. General description  
The 74LVC157A-Q100 is a quad 2-input multiplexer which select four bits of data from two  
sources under the control of a common select input (S). The four outputs present the  
selected data in the true (non-inverted) form. The enable input (E) is active LOW. When  
pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other  
input conditions. Moving the data from two groups of registers to four common output  
buses is a common use of the 74LVC157A-Q100. The state of the common data select  
input (S) determines the particular register from which the data comes. It can also be used  
as function generator.  
It is useful for implementing highly irregular logic by generating any 4 of the 16 different  
functions of two variables with one variable common.  
The device is the logic implementation of a 4-pole, 2-position switch, where the position of  
the switch is determined by the logic levels applied to pin S.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V applications.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
5 V tolerant inputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC157AD-Q100  
40 C to +125 C  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74LVC157ADB-Q100 40 C to +125 C  
74LVC157APW-Q100 40 C to +125 C  
74LVC157ABQ-Q100 40 C to +125 C  
SSOP16  
TSSOP16  
plastic shrink small outline package; 16 leads;  
body width 5.3 mm  
SOT338-1  
plastic thin shrink small outline package; 16 leads; SOT403-1  
body width 4.4 mm  
DHVQFN16 plastic dual In-line compatible thermal enhanced  
very thin quad flat package; no leads; 16  
SOT763-1  
terminals; body 2.5 3.5 0.85 mm  
4. Functional diagram  
1
G1  
15  
EN  
2
1
1
MUX  
4
7
9
3
5
6
2
3
5
6
11 10 14 13  
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1  
1
S
E
11  
10  
15  
1Y  
4
2Y  
7
3Y  
9
4Y  
12  
14  
13  
12  
mna482  
mna481  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
1I0  
2
3
1Y  
2Y  
3Y  
4Y  
4
7
1I1  
2I0  
2I1  
3I0  
3I1  
4I0  
5
6
MULTIPLEXER  
OUTPUTS  
SELECTOR  
11  
10  
14  
9
12  
13 4I1  
S
1
E
mna483  
15  
Fig 3. Functional diagram  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
2 of 17  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
S
E
1I1  
1Y  
2Y  
3Y  
1I0  
2I1  
2I0  
3I1  
3I0  
4I1  
4I0  
4Y  
mna484  
Fig 4. Logic diagram  
5. Pinning information  
5.1 Pinning  
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ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢅ  
(1) This is not a supply pin. The substrate is attached to this  
pad using conductive die attach material. There is no  
electrical or mechanical requirement to solder this pad.  
However, if it is soldered, the solder land should remain  
floating or be connected to GND.  
Fig 5. Pin configuration for SO16 and (T)SSOP16  
Fig 6. Pin configuration for DHVQFN16  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
3 of 17  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
5.2 Pin description  
Table 2.  
Symbol  
S
Pin description  
Pin  
1
Description  
common data select input  
data input from source 0  
data input from source 1  
multiplexer output  
1I0  
2
1I1  
3
1Y  
4
2I0  
5
data input from source 0  
data input from source 1  
multiplexer output  
2I1  
6
2Y  
7
GND  
3Y  
8
ground (0 V)  
9
multiplexer output  
3I1  
10  
11  
12  
13  
14  
15  
16  
data input from source 1  
data input from source 0  
multiplexer output  
3I0  
4Y  
4I1  
data input from source 1  
data input from source 0  
enable input (active LOW)  
supply voltage  
4I0  
E
VCC  
6. Functional description  
Table 3.  
Function table[1]  
Input  
Output  
E
H
L
L
L
L
S
X
L
nI0  
X
nI1  
X
nY  
L
L
X
L
L
H
X
X
H
L
H
H
L
X
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
4 of 17  
 
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
50  
0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0  
mA  
V
[1]  
[2]  
VI  
+6.5  
50  
VCC + 0.5  
50  
100  
-
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0  
VO = 0 V to VCC  
mA  
V
VO  
0.5  
-
IO  
output current  
mA  
mA  
mA  
C  
ICC  
supply current  
-
IGND  
Tstg  
Ptot  
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
500  
[3]  
Tamb = 40 C to +125 C  
mW  
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.  
[2] The output voltage ratings may be exceeded if the output current ratings are observed.  
[3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K.  
For (T)SSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K.  
For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
1.65  
1.2  
0
Typ  
Max  
Unit  
V
supply voltage  
-
-
-
-
-
-
-
3.6  
-
functional  
V
VI  
input voltage  
5.5  
VCC  
+125  
20  
V
VO  
output voltage  
0
V
Tamb  
t/V  
ambient temperature  
40  
0
C  
ns/V  
ns/V  
input transition rise and fall  
rate  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0
10  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
5 of 17  
 
 
 
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
9. Static characteristics  
Table 6.  
Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
Min Max  
Typ[1]  
1.08  
40 C to +125 C  
Min Max  
1.08  
Unit  
VIH  
HIGH-level  
VCC = 1.2 V  
-
-
-
-
-
-
V
V
V
V
V
V
V
V
input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.2 V  
0.65 VCC  
-
-
-
-
-
-
-
-
0.65 VCC  
1.7  
-
1.7  
2.0  
-
2.0  
VIL  
LOW-level  
-
-
-
-
0.12  
-
-
-
-
0.12  
input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VI = VIH or VIL  
0.35 VCC  
0.7  
0.35 VCC  
0.7  
0.8  
0.8  
VOH  
HIGH-level  
output  
IO = 100 A;  
VCC = 1.65 V to 3.6 V  
VCC 0.2  
-
-
VCC 0.3  
-
V
voltage  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 18 mA; VCC = 3.0 V  
IO = 24 mA; VCC = 3.0 V  
VI = VIH or VIL  
1.2  
1.8  
2.2  
2.4  
2.2  
-
-
-
-
-
-
-
-
-
-
1.05  
1.65  
2.05  
2.25  
2.0  
-
-
-
-
-
V
V
V
V
V
VOL  
LOW-level  
output  
voltage  
IO = 100 A;  
VCC = 1.65 V to 3.6 V  
-
-
0.2  
-
0.3  
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
-
-
-
-
-
-
0.45  
0.6  
-
-
-
-
-
0.65  
0.8  
V
-
V
-
0.4  
0.6  
V
-
0.55  
5  
0.8  
V
II  
input leakage VCC = 3.6 V; VI = 5.5 V or GND  
current  
0.1  
20  
A  
ICC  
ICC  
supply  
current  
VCC = 3.6 V; VI = VCC or GND;  
IO = 0 A  
-
-
0.1  
5
10  
-
-
40  
A  
A  
additional  
supply  
per input pin;  
500  
5000  
VCC = 2.7 V to 3.6 V;  
current  
VI = VCC 0.6 V; IO = 0 A  
CI  
input  
VCC = 0 V to 3.6 V;  
-
5.0  
-
-
-
pF  
capacitance VI = GND to VCC  
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
6 of 17  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
[2]  
[2]  
tpd  
propagation delay  
nI0, nI1 to nY; see Figure 8  
VCC = 1.2 V  
-
16  
4.8  
2.8  
2.9  
2.5  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.5  
1.0  
1.0  
10.2  
5.8  
5.9  
5.2  
1.0  
1.5  
1.0  
1.0  
11.8  
6.7  
7.5  
6.5  
VCC = 3.0 V to 3.6 V  
E to nY; see Figure 7  
VCC = 1.2 V  
-
17  
4.8  
2.8  
2.9  
2.6  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
0.5  
1.5  
1.0  
1.0  
12.8  
7.2  
7.8  
6.5  
0.5  
1.5  
1.0  
1.0  
14.7  
8.3  
10.0  
8.5  
VCC = 3.0 V to 3.6 V  
S to nY; see Figure 8  
VCC = 1.2 V  
-
16  
5.1  
3.0  
3.1  
2.7  
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
1.0  
1.5  
1.0  
1.0  
-
12.4  
7.0  
7.3  
6.3  
1.0  
1.0  
1.5  
1.0  
1.0  
-
14.3  
8.1  
9.5  
8.0  
1.5  
V
CC = 2.3 V to 2.7 V  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 3.0 V to 3.6 V  
per input; VI = GND to VCC  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
[3]  
[4]  
tsk(o)  
CPD  
output skew time  
power dissipation  
capacitance  
-
-
-
9.4  
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
12.8  
15.9  
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.  
[2] pd is the same as tPLH and tPHL  
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.  
[4] PD is used to determine the dynamic power dissipation (PD in W).  
t
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in V  
N = number of inputs switching  
(CL VCC2 fo) = sum of outputs  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
7 of 17  
 
 
 
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
11. Waveforms  
V
CC  
V
E input  
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
mna485  
V
OL  
VM = 1.5 V at VCC 2.7 V; VM = 0.5 VCC at VCC < 2.7 V.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 7. Enable input (E) to output (nY) propagation delays  
V
I
nI0, nI1, S  
input  
V
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
mna486  
V
OL  
VM = 1.5 V at VCC 2.7 V; VM = 0.5 VCC at VCC < 2.7 V.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 8. Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
8 of 17  
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
CC  
V
V
O
I
PULSE  
GENERATOR  
DUT  
R
T
C
L
R
L
001aaf615  
Test data is given in Table 8. Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
Fig 9. Test circuit for measuring switching times  
Table 8.  
Test data  
Supply voltage  
Input  
VI  
Load  
CL  
tr, tf  
RL  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
2 ns  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
30 pF  
50 pF  
50 pF  
1 k  
1 k  
500   
500   
500   
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
3.0 V to 3.6 V  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
9 of 17  
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
12. Package outline  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 10. Package outline SOT109-1 (SO16)  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
10 of 17  
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm  
SOT338-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
8
1
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.00  
0.55  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT338-1  
MO-150  
Fig 11. Package outline SOT338-1 (SSOP16)  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
11 of 17  
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT403-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
8
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.40  
0.06  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT403-1  
MO-153  
Fig 12. Package outline SOT403-1 (TSSOP16)  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
12 of 17  
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;  
16 terminals; body 2.5 x 3.5 x 0.85 mm  
SOT763-1  
B
A
D
A
A
1
E
c
detail X  
terminal 1  
index area  
C
terminal 1  
index area  
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16  
15  
10  
D
h
X
0
2.5  
scale  
5 mm  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.  
0.05 0.30  
0.00 0.18  
3.6  
3.4  
2.15  
1.85  
2.6  
2.4  
1.15  
0.85  
0.5  
0.3  
mm  
0.05  
0.1  
1
0.2  
0.5  
2.5  
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-10-17  
03-01-27  
SOT763-1  
- - -  
MO-241  
- - -  
Fig 13. Package outline SOT763-1 (DHVQFN16)  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
13 of 17  
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
13. Abbreviations  
Table 9.  
Acronym  
CDM  
DUT  
Abbreviations  
Description  
Charged Device Model  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
ESD  
HBM  
MM  
TTL  
Transistor-Transistor Logic  
Military  
MIL  
14. Revision history  
Table 10. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74LVC157A_Q100 v.2 20130502  
Product data sheet  
-
74LVC157A_Q100 v.1  
Modifications:  
74LVC157ADB-Q100 added.  
74LVC157A_Q100 v.1 20120807  
Product data sheet  
-
-
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
14 of 17  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
15.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
15 of 17  
 
 
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74LVC157A_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 2 May 2013  
16 of 17  
 
 
74LVC157A-Q100  
NXP Semiconductors  
Quad 2-input multiplexer  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
6
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 16  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 2 May 2013  
Document identifier: 74LVC157A_Q100  
 

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