74LVC161PW,118 [NXP]
74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP 16-Pin;
| 型号： | 74LVC161PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP 16-Pin 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC161
Presettable synchronous 4-bit
binary counter; asynchronous reset
Product specification
2004 Mar 30
Supersedes data of 1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
FEATURES
is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (pin CP). The
outputs (pins Q0 to Q3) of the counters may be preset to a
HIGH-level or a LOW-level. A LOW-level at the parallel
enable input (pin PE) disables the counting action and
causes the data at the data inputs (pins D0 to D3) to be
loaded into the counter on the positive-going edge of the
clock (provided that the set-up and hold time requirements
for PE are met). Preset takes place regardless of the levels
at count enable inputs (pins CEP and CET). A LOW-level
at the master reset input (pin MR) sets all four outputs of
the flip-flops (pins Q0 to Q3) to LOW-level regardless of
the levels at input pins CP, PE, CET and CEP (thus
providing an asynchronous clear function).
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. JESD8B/JESD36
• Asynchronous reset
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• ESD protection:
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (pins CEP and CET)
must be HIGH to count. The CET input is fed forward to
enable the terminal count output (pin TC). The TC output
thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH-level output of Q0.
This pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by tPHL (propagation delay CP to TC) and tsu
(set-up time CEP to CP) according to the following
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC161 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
1
formula:fmax
=
------------------------------------
tPHL(max) + tsu
The 74LVC161 is a synchronous presettable binary
counter which features an internal look-head carry and can
be used for high-speed counting. Synchronous operation
2004 Mar 30
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
propagation delay
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
CL = 50 pF; VCC = 3.3 V
CP to Qn
3.9
4.5
3.5
4.7
3.3
200
5.0
18
ns
ns
ns
ns
ns
CP to TC
MR to Qn
MR to TC
CET to TC
fclk(max)
CI
maximum clock frequency
input capacitance
power dissipation capacitance per gate
MHz
pF
CPD
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
ORDERING INFORMATION
TYPE NUMBER
TEMPERATURE
RANGE
PINS
PACKAGE MATERIAL
CODE
74LVC161D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
16
16
16
16
SO16
plastic
plastic
plastic
plastic
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74LVC161DB
74LVC161PW
74LVC161BQ
SSOP16
TSSOP16
DHVQFN16
2004 Mar 30
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
OPERATING
MODES
MR
CP
CEP
CET
PE
Dn
Qn
TC
Reset (clear)
Parallel load
L
X
↑
X
X
X
h
l
X
X
X
h
X
l
X
l
X
l
L
L
L
L
*
H
H
H
H
H
↑
l
h
X
X
X
H
Count
↑
h
h
h
count
qn
*
Hold
(do nothing)
X
X
*
X
qn
L
Note
1. * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level.
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock
transition.
X = don’t care.
↑ = LOW-to-HIGH clock transition.
PINNING
PIN
SYMBOL
DESCRIPTION
synchronous master reset (active LOW)
1
2
MR
CP
D0
D1
D2
D3
clock input (LOW-to-HIGH, edge-triggered)
data input
3
4
data input
5
data input
6
data input
7
CEP
GND
PE
count enable inputs
ground (0 V)
8
9
parallel enable input (active LOW)
count enable carry input
flip-flop output
10
11
12
13
14
15
16
CET
Q3
Q2
flip-flop output
Q1
flip-flop output
Q0
flip-flop output
TC
terminal count output
supply voltage
VCC
2004 Mar 30
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
V
MR
1
handbook, halfpage
CC
16
handbook, halfpage
2
3
15 TC
CP
V
MR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
CP
D0
TC
D0
14
Q0
Q0
Q1
D1
D2
D3
4
5
6
7
13 Q1
D1
(1)
GND
161
12
11
10
Q2
Q2
D2
D3
Q3
Q3
CET
PE
CEP
GND
CET
CEP
8
9
MNA904
GND PE
Top view
MNA980
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
1
9
7
handbook, halfpage
CTR4
R
15
handbook, halfpage
M1
G3
G4
TC
10
2
14
13
12
11
3
4
5
6
9
D0
D1
D2
D3
PE
Q0
Q1
Q2
Q3
C2 /1,3,4+
14
13
12
11
3
4
5
6
1,2D
CEP CET CP MR
15
4 CT = 15
MNA905
7
10
2
1
MNA906
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 30
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
3
4
5
6
handbook, halfpage
D0 D1 D2 D3
handbook, halfpage
0
1
2
3
4
5
6
7
PE
9
PARALLEL LOAD
CIRCUITRY
15
14
13
12
CET
10
TC
15
CEP
7
BINARY
COUNTER
CP
2
MR
1
11
10
9
8
Q0 Q1 Q2 Q3
14 13 12 11
MNA908
MNA907
Fig.5 Functional diagram.
Fig.6 State diagram.
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
12
13
14
15
0
1
2
count
inhibit
reset
preset
MNA909
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.
Fig.7 Timing sequence.
2004 Mar 30
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
D1
D2
D3
D0
CET
CEP
PE
FF0
FF1
FF2
FF3
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
Q
Q
Q
Q
R
R
R
R
D
D
D
D
CP
MR
Q0
TC
Q3
Q1
Q2
MNA910
Fig.8 Logic diagram.
7
2004 Mar 30
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.7
MAX.
3.6
UNIT
VCC
for maximum speed performance
for low voltage applications
V
1.2
0
3.6
5.5
VCC
+125
20
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
tr, tf
operating temperature
input rise and fall times
in free-air
−40
0
°C
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
note 1.
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
−
TYP.
MAX.
+6.5
UNIT
VCC
IIK
−
V
input diode current
input voltage
VI < 0 V
note 2
−50
−
−
mA
V
VI
−0.5
−
+6.5
−
IOK
VO
IO
output diode current
output voltage
VO > VCC or VO < 0 V
note 2
±50
−
mA
−0.5
−
VCC + 0.5 V
output source of sink current
VO = 0 V to VCC
±50
±100
−
−
mA
ICC, IGND VCC or GND current
−
−
mA
°C
Tstg
Ptot
storage temperature
power dissipation
−65
−
+150
Tamb = −40 °C to +125 °C; note 3
500
−
mW
Notes
1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and
functional operation of the device at these or any other condition beyond those indicated under “Recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
2004 Mar 30
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-level input
voltage
1.2
VCC
2.0
−
−
−
−
−
−
−
V
V
V
V
2.7 to 3.6
1.2
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
VCC − 0.2
VCC − 0.5
VCC − 0.6
VCC − 0.8
VCC
−
−
−
−
−
V
V
V
V
3.0
−
3.0
−
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
GND
−
0.2
0.4
0.55
±5
V
V
V
IO = 24 mA
3.0
−
ILI
input leakage
current
VI = 5.5 V or GND 3.6
±0.1
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND; 3.6
IO = 0 A
−
−
0.1
5
10
additional quiescent VI =VCC − 0.6 V;
2.7 to 3.6
500
supply current per
input pin
IO = 0 A
2004 Mar 30
9
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input
voltage
1.2
VCC
2.0
−
−
−
−
−
−
−
V
V
V
V
2.7 to 3.6
1.2
VIL
LOW-level input
voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
VCC − 0.3
VCC − 0.65
VCC − 0.75
VCC − 1
−
−
−
−
−
−
−
−
V
V
V
V
3.0
3.0
VOL
LOW-level output
voltage
2.7 to 3.6
2.7
−
−
−
−
−
−
−
−
0.3
0.6
0.8
±20
V
V
V
IO = 24 mA
3.0
ILI
input leakage
current
VI = 5.5 V or GND 3.6
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND; 3.6
IO = 0 A
−
−
−
−
40
additional quiescent VI =VCC − 0.6 V;
2.7 to 3.6
5000
supply current per
input pin
IO = 0 A
Note
1. Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Mar 30
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
WAVEFORMS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH propagation delay CP to Qn
propagation delay CP to TC
see Figs 9 and 14
see Figs 9 and 14
1.2
−
17
−
ns
2.7
1.5
1.5
−
−
7.2
7.3
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
3.0 to 3.6
1.2
3.9(2)
20
2.7
1.5
1.5
−
−
7.8
7.8
−
3.0 to 3.6
1.2
4.5(2)
propagation delay CET to TC see Figs 10 and 14
propagation delay MR to Qn see Figs 11 and 14
propagation delay MR to TC see Figs 11 and 14
16
2.7
1.5
1.5
−
−
6.5
6.0
−
3.0 to 3.6
1.2
3.3(2)
tPHL
17
2.7
1.5
1.5
−
−
7.1
6.4
−
3.0 to 3.6
1.2
3.5(2)
18
2.7
1.5
1.5
5.0
4.0
4.0
3.0
0.0
0.5
3.0
2.5
3.5
3.0
5.5
5.0
0.0
0.5
150
150
−
−
8.6
8.0
−
3.0 to 3.6
2.7
4.7(2)
tW
clock pulse width
HIGH or LOW
see Fig.9
−
3.0 to 3.6
2.7
1.2(2)
−
1.6(2)
−
master reset width LOW
removal time MR to CP
set-up time Dn to CP
see Fig.11
see Fig.11
see Fig.12
see Fig.12
see Fig.13
see Figs 12 and 13
see Fig.9
−
3.0 to 3.6
2.7
−
trem
−
−
3.0 to 3.6
2.7
0.0(2)
−
1.0(2)
−
tsu
−
3.0 to 3.6
2.7
−
set-up time PE to CP
−
−
3.0 to 3.6
2.7
1.2(2)
−
2.1(2)
−
set-up time CEP, CET to CP
−
3.0 to 3.6
2.7
−
th
hold time Dn, PE, CEP, CET
to CP
−
−
3.0 to 3.6
2.7
0.0(2)
−
200(2)
−
fclk(max)
maximum clock frequency
−
3.0 to 3.6
3.0 to 3.6
−
tsk(0)
skew
note 3
−
1.0
2004 Mar 30
11
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
CONDITIONS
WAVEFORMS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 °C to +125 °C
tPHL/tPLH propagation delay CP to Qn
see Figs 9 and 14
see Figs 9 and 14
1.2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
2.7
1.5
1.5
−
9.0
9.5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
3.0 to 3.6
1.2
propagation delay CP to TC
2.7
1.5
1.5
−
10.0
10.0
−
3.0 to 3.6
1.2
propagation delay CET to TC see Figs 10 and 14
propagation delay MR to Qn see Figs 11 and 14
propagation delay MR to TC see Figs 11 and 14
2.7
1.5
1.5
−
8.5
7.5
−
3.0 to 3.6
1.2
tPHL
2.7
1.5
1.5
−
9.0
8.0
−
3.0 to 3.6
1.2
2.7
1.5
1.5
5.0
4.0
4.0
3.0
0.0
0.5
3.0
2.5
3.5
3.0
5.5
5.0
0.0
0.5
150
150
−
11.0
10.0
−
3.0 to 3.6
2.7
tW
clock pulse width
HIGH or LOW
see Fig.9
3.0 to 3.6
2.7
−
master reset width LOW
removal time MR to CP
set-up time Dn to CP
see Fig.11
see Fig.11
see Fig.12
see Fig.12
see Fig.13
see Figs 12 and 13
see Fig.9
−
3.0 to 3.6
2.7
−
trem
−
3.0 to 3.6
2.7
−
tsu
−
3.0 to 3.6
2.7
−
set-up time PE to CP
−
3.0 to 3.6
2.7
−
set-up time CEP, CET to CP
−
3.0 to 3.6
2.7
−
th
hold time Dn, PE, CEP, CET
to CP
−
3.0 to 3.6
2.7
−
fclk(max)
maximum clock frequency
−
3.0 to 3.6
3.0 to 3.6
−
tsk(0)
skew
note 3
1.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 Mar 30
12
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
AC WAVEFORMS
1/f
max
V
I
CP input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
V
Qn, TC output
V
M
OL
MNA911
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.9 Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock
frequency.
V
handbook, halfpage
I
CET input
V
M
GND
t
t
PLH
PHL
V
OH
TC output
V
M
V
OL
MNA912
V
M = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.10 Input (CET) to output (TC) propagation delays.
13
2004 Mar 30
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
V
I
V
MR input
M
GND
t
rem
t
W
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn, TC output
M
V
OL
MNA913
Fig.11 Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master
reset to clock (CP) removal times.
V
I
V
PE input
M
t
GND
t
su
su
t
t
h
h
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
MNA914
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.12 Set-up and hold times for the input (Dn) and parallel enable input (PE).
14
2004 Mar 30
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
V
I
V
CEP, CET input
M
GND
t
t
h
h
t
t
su
su
V
I
V
CP input
M
GND
MNA915
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.13 CEP and CET set-up and hold times.
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
CL
RL
1.2 V
2.7 V
VCC
50 pF
50 pF
50 pF
500 Ω(1)
500 Ω
open
open
open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
3.0 V to 3.6 V
500 Ω
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.14 Load circuitry for switching times.
2004 Mar 30
15
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
2004 Mar 30
16
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
2004 Mar 30
17
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
2004 Mar 30
18
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
2004 Mar 30
19
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74LVC161
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 30
20
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp21
Date of release: 2004 Mar 30
Document order number: 9397 750 10505
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