74LVC162374ADGG-T [NXP]
IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver;
| 型号： | 74LVC162374ADGG-T |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver 触发器 |
| 文件： | 总16页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC162374A; 74LVCH162374A
16-bit edge triggered D-type
flip-flop with 30 Ω series termination
resistors; 5 V input/output tolerant;
3-state
Product specification
1999 Aug 05
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
74LVC162374A;
termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374A
FEATURES
DESCRIPTION
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate
D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.
A clock (CP) input and an output enable (OE) are provided for each octal.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
• 5 V tolerant input/output for
interfacing with 5 V logic
The flip-flops will store the state of their individual D-inputs that meet the set-up
and hold time requirements on the LOW-to-HIGH CP transition.
• Wide supply voltage range of
1.2 to 3.6 V
• Complies with JEDEC standard
no. 8-1A
When OE is LOW, the contents of the flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
• CMOS low power consumption
• MULTIBYTE flow-through
standard pin-out architecture
The 74LVCH162374A bus hold data inputs eliminates the need for external pull
up resistors to hold unused inputs.
• Low inductance multiple power and
ground pins for minimum noise and
ground bounce
The 74LVC(H)162374A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.
• Direct interface with TTL levels
• All data inputs have bus hold
(74LVCH162374A only)
• High impedance when VCC = 0
• Power off disables outputs,
permitting live insertion.
FUNCTION TABLE
See note 1.
INPUTS
nCP
OUTPUTS
Q0 to Q7
INTERNAL
FLIP-FLOPS
OPERATION MODES
nOE
nDn
L
L
↑
↑
↑
↑
l
L
H
L
L
H
Z
Z
Load and read register
h
l
H
H
Latch register and disable outputs
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
1999 Aug 05
2
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
3.8
UNIT
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 50 pF; VCC = 3.3 V
ns
fmax
CI
150
5.0
30
MHz
pF
CPD
power dissipation capacitance per
flip-flop
VCC = 3.3 V; note 1
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
ORDERING INFORMATION
OUTSIDE NORTH
PACKAGE
PINS PACKAGE MATERIAL
NORTH AMERICA
TEMPERATURE
AMERICA
CODE
RANGE
74LVC162374ADL
74LVC162374ADGG
74LVCH162374ADL
VC162374A DL
VC162374A DGG
VCH162374A DL
−40 to +85 °C
48
48
48
48
SSOP
TSSOP
SSOP
plastic
plastic
plastic
plastic
SOT370-1
SOT362-1
SOT370-1
SOT362-1
74LVCH162374ADGG VCH162374A DGG
TSSOP
PINNING
PIN
SYMBOL
DESCRIPTION
1
1OE
1Q0 to 1Q7
4, 10, 15, 21, 28, 34, 39, 45 GND
7, 18, 31, 42 VCC
13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7
output enable input (active LOW)
3-state flip-flop outputs
ground (0 V)
2, 3, 5, 6, 8, 9, 11, 12
DC supply voltage
3-state flip-flop outputs
output enable input (active LOW)
clock input
24
25
2OE
2CP
36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7
47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7
data inputs
data inputs
48
1CP
clock input
1999 Aug 05
3
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
handbook, halfpage
1OE
1CP
1
2
3
4
5
6
7
8
9
48
47
46
1Q
0
1D
0
1Q
1
1D
1
1
24
handbook, halfpage
GND
45 GND
1OE
2OE
1Q
2
1D
1D
V
44
43
42
41
40
2
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1Q
3
3
3
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
5
V
CC
CC
6
1Q
4
1D
4
5
8
1Q
5
1D
9
GND 10
39 GND
11
12
13
14
16
17
19
20
22
23
1Q
1Q
2Q
2Q
1D
1D
2D
2D
11
12
13
14
38
37
36
35
6
7
0
1
6
7
0
1
162374A
GND 15
34 GND
2Q
2Q
2D
2D
V
16
17
18
19
20
33
32
31
30
29
2
3
2
3
1CP
2CP
V
CC
CC
2Q
2D
4
5
4
5
MNA434
48
25
2Q
2D
GND 21
28 GND
2Q
2Q
2D
2D
22
23
27
26
25
6
7
6
7
2CP
2OE 24
MNA433
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1999 Aug 05
4
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
1D
1Q
2D
0
2Q
0
D
Q
D
Q
0
0
CP
CP
FF1
FF2
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
MNA435
Fig.3 Logic diagram.
1
48
24
25
handbook, halfpage
1EN
C3
1OE
1CP
2OE
2CP
2EN
C2
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D
0
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
1D
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1D
1
V
5
handbook, halfpage
CC
1D
2
6
1D
3
8
1D
4
9
input
to internal circuit
1D
5
11
12
13
14
16
17
19
20
22
23
1D
6
1D
7
MNA428
2D
0
2D
2
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
MNA436
Fig.4 IEC logic symbol.
Fig.5 Bus hold circuit.
1999 Aug 05
5
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
MAX.
VCC
for max. speed performance
for low-voltage applications
DC input voltage range
DC output voltage range
output HIGH or LOW state
3-state
2.7
3.6
V
V
V
1.2
0
3.6
5.5
VI
VO
0
VCC
5.5
V
0
V
Tamb
tr, tf
operating ambient temperature
see DC and AC characteristics per
device
−40
+85
°C
input rise and fall times
VCC = 1.2 to 2.7 V
0
0
20
10
ns/V
ns/V
VCC = 2.7 to 3.6 V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
DC input diode current
DC input voltage
VI < 0
note 1
−
−50
+5.5
±50
mA
V
VI
−0.5
−
IOK
VO
DC output diode current
DC output voltage
VO > VCC or VO < 0
mA
output HIGH or LOW
output 3-state
note 1
−0.5
−0.5
−
V
CC + 0.5
V
note 1
+6.5
±50
±100
+150
500
V
IO
DC output diode current
VO = 0 to VCC
mA
mA
°C
mW
I
GND, ICC DC VCC or GND current
−
Tstg
Ptot
storage temperature
−65
−
power dissipation plastic shrink
mini-pack (SSOP and TSSOP)
above 60 °C derate linearly with
5.5 mW/K
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1999 Aug 05
6
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
T
amb (°C)
−40 to +85
TYP.(1) MAX.
SYMBOL
PARAMETER
UNIT
OTHER
VCC (V)
MIN.
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
1.2
2.7 to 3.6 2.0
1.2
2.7 to 3.6 −
VCC
−
−
−
−
−
−
V
−
−
GND
0.8
−
V
V
VOH
HIGH-level output voltage VI = VIH or VIL; IO = −6 mA 2.7
VCC − 0.5
VI = VIH or VIL;
3.0
VCC − 0.2 VCC
−
IO = −100 µA
VI = VIH or VIL;
3.0
VCC − 0.8
−
−
IO = −12 mA
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL; IO = 6 mA 2.7
−
−
−
−
0.40
0.20
V
VI = VIH or VIL;
3.0
IO = 100 µA
VI = VIH or VIL; IO = 12 mA 3.0
VI = 5.5 V or GND; note 2 3.6
−
−
−
−
0.55
±5
II
±0.1
0.1
µA
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
3.6
±5
VO = 5.5 V or GND
Ioff
power off leakage supply
quiescent supply current
VI or VO = 5.5 V
0.0
3.6
−
−
0.1
0.1
5
±10
20
µA
µA
µA
ICC
∆ICC
VI = VCC or GND; IO = 0
additional quiescent supply VI = VCC − 0.6 V; IO = 0
2.7 to 3.6 −
500
current per control pin
IBHL
bus hold LOW sustaining
current
VI = 0.8 V; notes 3,
4 and 5
3.0
3.0
3.6
3.6
75
−75
−
−
−
−
−
−
−
−
µA
µA
µA
µA
IBHH
bus hold HIGH sustaining
current
VI = 2.0 V; notes 3,
4 and 5
IBHLO
IBHHO
bus hold LOW overdrive
current
VI = 0.8 V; notes 3,
4 and 6
500
bus hold HIGH overdrive
current
VI = 0.8 V; notes 3,
4 and 6
−500
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH162374A) only.
4. For data inputs only, control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1999 Aug 05
7
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; Tamb = −40 to +85 °C.
LIMITS
VCC = 3.3 V ±0.3 V
MIN.
TYP.(1) MAX. MIN. MAX.
SYMBOL
PARAMETER
WAVEFORMS
VCC = 2.7 V
UNIT
t
t
t
PHL/tPLH
PZH/tPZL
PHZ/tPLZ
propagation delay
nCP to nQn
see Figs 6 and 9
see Figs 8 and 9
see Figs 8 and 9
1.5
1.5
1.5
3
3.8
4.1
3.7
1.5
6.2
7.1
5.2
−
1.5
1.5
1.5
3.0
7.2
8.1
6.2
−
ns
ns
ns
ns
3-state output enable
time nOE to nQn
3-state output disable
time nOE to nQn
tW
nCP pulse width HIGH or see Fig.6
LOW
tsu
th
set-up time nDn to nCP
hold time nDn to nCP
see Fig.7
see Fig.7
see Fig.6
2.0
0.3
−0.3
−
−
−
−
2.0
1.5
80
−
−
−
ns
+1.5
100
ns
fmax
maximum clock pulse
frequency
MHz
Note
1. Typical values at VCC = 3.3 V and Tamb = 25 °C.
1999 Aug 05
8
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
AC WAVEFORMS
1/f
max
V
I
nCP INPUT
V
t
V
M
M
GND
t
W
t
PHL
PLH
V
OH
V
nQ OUTPUT
M
n
V
OL
MNA437
Fig.6 Clock input (nCP) to output (nQn) propagation delay, the clock pulse width and the maximum clock pulse
frequency.
V
I
V
nCP INPUT
M
GND
t
t
su
su
t
t
h
h
V
I
V
nD INPUT
n
M
GND
V
OH
V
nQ OUTPUT
n
M
V
OL
MNA438
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.7 Data set-up and hold times for the nDn input to the nCP input.
9
1999 Aug 05
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
V
I
nOE INPUT
V
M
t
GND
t
PLZ
PZL
V
CC
nQ OUTPUT
n
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
nQ OUTPUT
n
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA432
Fig.8 3-state enable and disable times.
S
2 × V
1
CC
open
GND
V
CC
R
L
500 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA296
Definitions for test circuit:
TEST
S1
open
RL = Load resistor; see Chapter “AC Characteristics”.
VCC
VI
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
CL = Load capacitance including jig and probe capacitance
(see Chapter “AC Characteristics”).
<2.7 V
VCC
2 × VCC
RT = Termination resistance should be equal to the output
impedance Zo of the pulse generator.
2.7 - 3.6 V 2.7 V
GND
Fig.9 Load circuitry for switching times.
10
1999 Aug 05
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-11-02
95-02-04
SOT370-1
MO-118AA
1999 Aug 05
11
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-02-03
95-02-10
SOT362-1
MO-153ED
1999 Aug 05
12
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Aug 05
13
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Aug 05
14
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
NOTES
1999 Aug 05
15
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/01/pp16
Date of release: 1999 Aug 05
Document order number: 9397 750 05975
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