74LVC16373ADGG [NXP]
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state; 16位D型透明锁存器具有5 V容限输入/输出;三态
| 型号： | 74LVC16373ADGG |
| 厂家： | 
NXP |
| 描述： | 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state |
| 文件： | 总17页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
Product specification
2003 Dec 08
Supersedes data of 2002 Oct 02
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74LVC(H)16373A is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One Latch Enable
(LE) input and one Output Enable (OE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices. In 3-state operation, outputs can handle 5 V.
These features allow the use of these devices in a mixed
3.3 and 5 V environment.
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
The 74LVC(H)16373A consists of 2 sections of eight
D-type transparent latches with 3-state true outputs. When
LE is HIGH, data at the Dn inputs enter the latches. In this
condition the latches are transparent, i.e., a latch output
will change each time its corresponding D-input changes.
• All data inputs have bushold (74LVCH16373A only)
• High-impedance when VCC = 0 V.
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
• Specified from −40 to +85 °C and −40 to +125 °C.
The 74LVCH16373A bushold data inputs eliminates the
need for external pull up resistors to hold unused inputs.
FUNCTION TABLE
Per section of eight bits; note 1
INPUT
INTERNAL
LATCHE
OUTPUT
nQ0 to nQ7
OPERATING MODES
nOE
nLE
H
H
L
nDn
Enable and read register (transparent mode)
L
L
L
H
l
L
H
L
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Z
Latch register and disable outputs
H
H
L
L
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
2003 Dec 08
2
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
3.0
UNIT
propagation delay Dn to Qn
propagation delay LE to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
input capacitance
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
ns
ns
ns
ns
pF
3.4
3.5
3.9
5.0
tPZH/tPZL
PHZ/tPLZ
t
CI
CPD
power dissipation per latch
VCC = 3.3 V; notes 1 and 2
outputs enabled
15
11
pF
pF
outputs disabled
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
a) PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacity in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC16373ADGG
74LVCH16373ADGG
74LVC16373ADL
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
48
48
48
48
TSSOP48
TSSOP48
SSOP48
SSOP48
plastic
plastic
plastic
plastic
SOT362-1
SOT362-1
SOT370-1
SOT370-1
74LVCH16373ADL
2003 Dec 08
3
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
PINNING
SYMBOL
1D1
PIN
DESCRIPTION
SYMBOL
1OE
PIN
DESCRIPTION
46
47
48
data input
data input
1
output enable input
(active LOW)
1D0
1LE
latch enable input
(active HIGH)
1Q0
1Q1
GND
2
3
data output
data output
4, 10, 15, 21, 28, ground (0 V)
34, 39, 45
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2OE
5
data output
data output
supply voltage
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
6
7, 18, 31, 42
8
1
2
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
V
1OE
1Q0
1Q1
GND
1Q2
1Q3
9
11
12
13
14
16
17
19
20
22
23
24
3
4
5
6
V
CC
7
42
CC
8
41 1D4
40 1D5
39 GND
1Q4
1Q5
GND
1Q6
1Q7
9
10
11
12
1D6
1D7
2D0
2D1
GND
2D2
2D3
38
37
36
35
34
33
32
31
30
29
28
27
26
25
16373A
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
output enable input
(active LOW)
2LE
25
latch enable input
(active HIGH)
V
CC
V
CC
18
2D4
2D5
GND
2D6
2D7
2LE
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
2D7
2D6
2D5
2D4
2D3
2D2
2D1
2D0
1D7
1D6
1D5
1D4
1D3
1D2
26
27
29
30
32
33
35
36
37
38
40
41
43
44
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
mgu767
Fig.1 Pin configuration SSOP48 and TSSOP48.
2003 Dec 08
4
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
1D0
1Q0
2D0
2Q0
D
Q
D
Q
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
MGU769
Fig.2 Logic diagram.
1
48
24
25
1
24
handbook, halfpage
handbook, halfpage
1EN
C3
1OE
1LE
2OE
2LE
1OE
2OE
2EN
C4
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1Q
0
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
3D
1
6
5
8
6
9
8
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
MGU768
MGU770
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2003 Dec 08
5
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
V
handbook, halfpage
CC
data input
to internal circuit
MGU771
Fig.5 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
for maximum speed performance 2.7
V
for low voltage applications
1.2
0
3.6
5.5
VCC
5.5
+125
20
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
in free-air
−40
0
°C
ns/V
ns/V
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
mA
V
output HIGH or LOW state; note 1 −0.5
VCC + 0.5
+6.5
±50
output 3-state; note 1
VO = 0 to VCC
−0.5
−
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
500
−65
−
Ptot
Tamb = −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of Ptot derate linearly with 5.5 mW/K.
2003 Dec 08
6
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
DC CHARACTERISTICS
Al recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
1.2
VCC
−
−
−
−
−
V
V
V
V
2.7 to 3.6 2.0
−
LOW-level input voltage
1.2
−
−
GND
0.8
2.7 to 3.6
VOH
HIGH-level output voltage VI = VIH or VIL:
IO = −100 µA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.2
CC − 0.5
CC − 0.6
CC − 0.8
−
−
−
−
−
−
−
−
V
V
V
V
IO = −12 mA
IO = −18 mA
3.0
IO = −24 mA
LOW-level output voltage VI = VIH or VIL:
IO = 100 µA
3.0
VOL
2.7 to 3.6
2.7
−
−
−
−
−
−
0.20
0.40
0.55
±5
V
IO = 12 mA
−
V
IO = 24 mA
3.0
−
V
ILI
input leakage current
VI = 5.5 V or GND; note 3
3.6
±0.1
±0.1
µA
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
3.6
±5
current
VO = 5.5 V or GND; note 3
Ioff
power off leakage current VI or VO = 5.5 V
quiescent supply current VI = VCC or GND; IO = 0
0
−
−
−
±0.1
0.1
5(2)
±10
20
µA
µA
µA
ICC
∆ICC
3.6
additional quiescent
supply current per input
pin
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
500
IBHL
bushold LOW sustaining VI = 0.8 V; notes 4 and 5
current
3.0
3.0
3.6
3.6
75
−
−
−
−
−
−
−
−
µA
µA
µA
µA
IBHH
bushold HIGH sustaining VI = 2.0 V; notes 4 and 5
current
−75
500
−500
IBHLO
IBHHO
bushold LOW overdrive
current
notes 4 and 6
bushold HIGH overdrive
current
notes 4 and 6
2003 Dec 08
7
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
TEST CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input voltage
1.2
VCC
−
−
−
−
−
V
V
V
V
2.7 to 3.6 2.0
−
LOW-level input voltage
1.2
−
−
GND
0.8
2.7 to 3.6
VOH
HIGH-level output voltage VI = VIH or VIL:
IO = −100 µA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.3
−
−
−
−
−
V
V
V
V
IO = −12 mA
CC − 0.65 −
CC − 0.75 −
IO = −18 mA
3.0
IO = −24 mA
LOW-level output voltage VI = VIH or VIL:
IO = 100 µA
3.0
CC − 1
−
VOL
2.7 to 3.6
2.7
−
−
−
−
−
−
−
−
−
−
0.3
0.6
0.8
±20
±20
V
IO = 12 mA
V
IO = 24 mA
3.0
V
ILI
input leakage current
VI = 5.5 V or GND; note 3
3.6
µA
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
3.6
current
VO = 5.5 V or GND; note 3
Ioff
power off leakage current VI or VO = 5.5 V
quiescent supply current VI = VCC or GND; IO = 0
0
−
−
−
−
−
−
±20
µA
µA
ICC
∆ICC
3.6
80
additional quiescent
supply current per input
pin
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
5000 µA
IBHL
bushold LOW sustaining VI = 0.8 V; notes 4 and 5
current
3.0
3.0
3.6
3.6
60
−
−
−
−
−
−
−
−
µA
µA
µA
µA
IBHH
bushold HIGH sustaining VI = 2.0 V; notes 4 and 5
current
−60
500
−500
IBHLO
IBHHO
bushold LOW overdrive
current
notes 4 and 6
bushold HIGH overdrive
current
notes 4 and 6
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Measured at VCC = 3.3 V.
3. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
4. Valid for data inputs of bushold parts (LVCH16373A) only. For data inputs only; control inputs do not have a bushold
circuit.
5. The specified sustaining current at the data inputs holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2003 Dec 08
8
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
Tamb = −40 to +85 °C; note1
tPHL/tPLH propagation delay Dn to Qn
propagation delay LE to Qn
see Fig 6 and 10 1.2
2.7
−
12
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
−
4.9
3.0 to 3.6 1.0
3.0(2) 4.4
see Fig 7 and 10 1.2
2.7
−
14
−
1.5
−
5.3
3.0 to 3.6 1.5
3.4(2) 4.8
tPZH/tPZL 3-state output enable time OE to Qn
tPHZ/tPLZ 3-state output disable time OE to Qn
see Fig 8 and 10 1.2
2.7
−
18
−
1.5
−
5.7
3.0 to 3.6 1.0
3.5(2) 4.9
see Fig 8 and 10 1.2
2.7
−
11
−
1.5
−
6.3
3.0 to 3.6 1.5
3.9(2) 5.4
tW
LE pulse width HIGH
set-up time Dn to LE
hold time Dn to LE
skew
see Fig 7
see Fig 9
see Fig 9
note 3
1.2
2.7
−
−
−
3.0
−
−
3.0 to 3.6 3.0
2.0(2)
−
tsu
1.2
2.7
−
−
−
2.0
−
−
3.0 to 3.6 2.0
1.0(2)
−
th
1.2
2.7
−
−
−
0.9
−
−
3.0 to 3.6 0.9
3.0 to 3.6
−1.0(2)
−
tsk(0)
−
−
1.0
2003 Dec 08
9
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
amb = −40 to +125 °C
PARAMETER
MIN.
TYP. MAX. UNIT
T
tPHL/tPLH propagation delay Dn to Qn
see Fig 6 and 10
see Fig 7 and 10
see Fig 8 and 10
see Fig 8 and 10
see Fig 7
1.2
2.7
3.0 to 3.6 1.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
6.5
5.5
−
propagation delay LE to Qn
1.2
2.7
−
1.5
7.0
6.0
−
3.0 to 3.6 1.5
t
PZH/tPZL
3-state output enable time OE to Qn
3-state output disable time OE to Qn
LE pulse width HIGH
set-up time Dn to LE
1.2
2.7
−
1.5
7.5
6.5
−
3.0 to 3.6 1.0
tPHZ/tPLZ
1.2
2.7
−
1.5
8.0
7.0
−
3.0 to 3.6 1.5
tW
tsu
th
1.2
2.7
−
3.0
−
3.0 to 3.6 3.0
−
see Fig 9
1.2
2.7
−
−
2.0
−
3.0 to 3.6 2.0
−
hold time Dn to LE
see Fig 9
1.2
2.7
−
−
0.9
−
3.0 to 3.6 0.9
3.0 to 3.6
−
tsk(0)
skew
note 3
−
1.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction.
This parameter is guaranteed by design.
2003 Dec 08
10
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
AC WAVEFORMS
V
handbook, halfpage
I
V
V
M
Dn input
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
MGU772
V
OL
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
1.2 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.6 Input (Dn) to output (Qn) propagation delays.
V
handbook, halfpage
I
LE input
GND
V
t
V
V
M
M
M
t
W
t
PHL
PLH
V
OH
V
V
M
Qn output
M
V
OL
MGU773
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
1.2 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.7 Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays.
2003 Dec 08
11
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
V
I
OE input
V
M
V
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu775
INPUT
VX = VOL + 0.3 V at VCC ≥ 2.7 V.
VX = VOL + 0.1VCC at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V.
VY = VOH − 0.1VCC at VCC < 2.7 V.
VCC
VM
VI
tr = tf
1.2 V
2.7 V
0.5 × VCC VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
3.0 to 3.6 V
Fig.8 3-state enable and disable times.
V
I
V
Dn input
M
GND
t
t
h
h
t
t
su
su
V
I
V
LE input
M
GND
MGU774
INPUT
VCC
VM
VI
tr = tf
1.2 V
0.5 × VCC VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V
1.5 V
1.5 V
2.7 V
2.7 V
The shaded areas indicate when the input is permitted to change
for predictable performance.
3.0 to 3.6 V
Fig.9 Data set-up and hold times for the Dn input to the LE input.
12
2003 Dec 08
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.2 V
2.7 V
50 pF
50 pF
50 pF
500 Ω(1) open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
500 Ω
500 Ω
open
open
3.0 to 3.6 V
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.10 Load circuitry for switching times.
2003 Dec 08
13
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
PACKAGE OUTLINES
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
2003 Dec 08
14
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
2003 Dec 08
15
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
74LVC16373A;
74LVCH16373A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Dec 08
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/06/pp17
Date of release: 2003 Dec 08
Document order number: 9397 750 12347
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