74LVC169PWDH [NXP]
Presettable synchronous 4-bit up/down binary counter; 可预置同步4位向上/向下二进制计数器
| 型号： | 74LVC169PWDH |
| 厂家： | 
NXP |
| 描述： | Presettable synchronous 4-bit up/down binary counter |
| 文件： | 总14页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC169
Presettable synchronous 4-bit up/down
binary counter
specification
1998 May 20
Supersedes data of 1996 Aug 23
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
The 74LVC169 is a synchronous presettable binary counter which
features an internal lookahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Synchronous counting and loading
• Up/down counting
The outputs (Q to Q ) of the counters may be preset to a HIGH or
0
3
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D to D ) to be loaded into the counter on the positive-going edge
0
3
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q to Q ) to LOW level
0
3
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
• Modular 16 binary counter
• Two count enable inputs for n-bit cascading
• Built-in lookahead carry capability
• Presettable for programmable operation
• Positive-edge triggered clock
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The lookahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
DESCRIPTION
of a duration approximately equal to a HIGH level output of Q . This
0
The 74LVC169 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
1
_______________________________
f
=
max
tp
(max)
(CP to TC) + t (CEP to CP)
SU
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; T = T ꢀ 2.5ns
amb
R F
SYMBOL
PARAMETER
Propagation delay
CONDITIONS
C = 50 pF
TYPICAL
UNIT
L
CP to Q
CP to TC
CET to TC
V
CC
= 3.3V
5.0
6.5
5.3
n
t
/t
ns
PHL PLH
f
maximum clock frequency
input capacitance
200
5.0
42
MHz
pF
MAX
C
I
C
power dissipation capacitance per gate
notes 1 and 2
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C x V
x f +Σ (C x V
x f where:
D
PD
CC
i
L
CC o )
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
Σ (C x V
x f = sum of the outputs
L
CC
o )
2. The condition is V = GND to V
1
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVC169 D
DWG NUMBER
SOT109-1
16-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC169 D
74LVC169 DB
74LVC169 PW
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
74LVC169 DB
SOT338-1
74LVC169PW DH
SOT403-1
2
1998 May 20
853-1866 19421
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
U/D
CP
1
2
3
4
5
16
V
CC
1
U/D
CP
up/down control input
15 TC
clock input (LOW-to-HIGH,
edge-triggered)
2
14
13
12
11
D
0
Q
Q
Q
Q
0
1
2
3
D
1
3,4,5,6
D to D
0
data inputs
3
D
2
count enable inputs (active
LOW)
7
8
9
CEP
GND
PE
6
7
8
D
3
CEP
GND
10 CET
PE
ground (0V)
9
parallel enable input
(active LOW)
SF00766
count enable carry input
(active LOW)
10
14,13,12,11
15
CET
Q to Q
0
flip-flop outputs
3
LOGIC SYMBOL
terminal count output
(active LOW)
TC
3
4
5
6
16
V
CC
positive supply voltage
D
D
D
2
D
3
0
1
LOGIC SYMBOL (IEEE/IEC)
9
PE
1
2
7
U/D
CP
CTR DIV 16
TC
15
9
M1 [LOAD]
CEP
CET
M2 [COUNT]
1
M3 [UP]
10
Q
Q
Q
2
Q
3
0
1
M4 [DOWN]
10
15
3, 5 CT=15
4, 5 CT=0
G5
G6
7
2
14
13
12
11
2, 3, 5, 6+/C7
2, 4, 5, 6–
V
= Pin 16
CC
GND = Pin 8
SF00786
3
14
13
12
11
1, 7D
[1]
[2]
[4]
[8]
4
5
6
SF00787
3
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
STATE DIAGRAM
TYPICAL TIMING SEQUENCE
0
1
2
3
4
5
6
7
MR
PE
D0
D1
D2
D3
15
14
13
CP
CEP
CET
12
11
10
9
8
COUNT DOWN
COUNT UP
Q0
Q1
Q2
Q3
SF00788
FUNCTION TABLE
TC
12
13
14
15
0
1
2
INPUTS
CP U/D CEP CET PE
OUTPUTS
OPERATING
MODES
COUNT
INHIBIT
RESET PRESET
D
Q
TC
n
n
Parallel load
(Dn→Qn)
↑
↑
X
X
X
X
X
X
l
l
L
*
*
SY00069
X
X
H
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
Count Up
(increment)
Count
Up
h
l
l
l
l
l
h
h
X
X
*
*
↑
↑
Count Down
(decrement)
Count
Down
Hold
(do nothing)
X
X
h
X
X
h
h
X
X
q
*
↑
↑
n
X
q
n
H
H = High voltage level steady state
h
= High voltage level one setup time prior to the Low-to-High
clock transition
L
l
= Low voltage level steady state
= Low voltage level one setup time prior to the Low-to-High
clock transition
q
= Lower case letters indicate the state of the referenced output
prior to the Low-to-High clock transition
X = Don’t care
↑
*
= Low-to-High clock transition
= The TC is Low when CET is Low and the counter is at
Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is
(LLLL).
4
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
LOGIC DIAGRAM
3
D
Q
Q
D
0
14
CP
Q
0
4
D
Q
Q
D
1
13
CP
Q
1
D
Q
5
D
2
12
CP Q
Q
2
D
Q
6
D
3
11
CP Q
Q
3
9
PE
7
CEP
10
CET
2
CP
1
U/D
15
TC
V
= Pin 16
CC
GND = Pin 8
SF00789
5
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
APPLICATION
CP
U/D
PE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
PE
PE
PE
U/D
CP
PE
U/D
CP
U/D
CP
U/D
CP
TC
TC
TC
TC
CEP
CET
CEP
CET
CEP
CET
CEP
CET
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2 3
LEAST SIGNIFICANT
4-BIT COUNTER
MOST SIGNIFICANT
4-BIT COUNTER
SF00790
Synchronous multistage counting scheme
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
3.6
3.6
5.5
V
CC
V
V
I
V
V
V
O
DC output voltage range
0
V
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +6.5
–50
DC input diode current
DC input voltage
V t0
mA
V
I
V
I
Note 2
–0.5 to +5.5
"50
I
DC output diode current
DC output voltage
V
O
uV or V t 0
mA
V
OK
CC
O
V
O
Note 2
= 0 to V
CC
–0.5 to V +0.5
CC
I
O
DC output source or sink current
V
O
"50
"100
mA
mA
°C
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and
TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
P
TOT
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*1.0
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
V
= 3.0V; V = V or V I
= –12mA
I = –24mA
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
10
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
GND
V
OL
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND
"0.1
µA
µA
I
I
I
Quiescent supply current
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
7
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF; R = 500W; T
= –40_C to +85_C
r
f
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
V = 1.2V
CC
UNIT
1
MIN.
TYP
MAX.
MIN.
MAX.
TYP
propagation delay
CP to Q
t
t
t
t
/t
1
1
2
4
1
3
3
5
5
-
5.0
8.5
-
9.5
24
30
19
24
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
n
propagation delay
CP to TC
/t
-
6.5
5.3
5.7
1.2
1.0
1.2
2.8
2.1
10.8
-
12.8
PHL PLH
propagation delay
CET to TC
/t
-
8.7
-
9.7
PHL PLH
propagation delay
U/D to TC
/t
-
9.5
-
10.5
PHL PLH
clock pulse width
HIGH or LOW
t
4.0
2.5
3.0
5.5
4.5
-
-
-
-
-
5.0
3.0
3.5
6.5
5.5
-
-
-
-
-
W
su
su
su
su
set-up time
t
t
t
t
-
D
to CP
n
set-up time
to CP
-
PE
set-up time
U/D to CP
-
set-up time
-
CEP, CET to CP
hold time
t
3 and 5
1
0
*2.5
-
-
0
-
-
-
-
ns
h
D , PE, CEP, CET,
U/D to CP
n
maximum clock pulse
frequency
f
125
200
110
MHz
max
NOTE:
1. These typical values are measured at
V
= 3.3V and T
= 25°C.
CC
amb
8
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
AC WAVEFORMS
V
V
V
= 1.5 V at V w 2.7 V
M
CC
= 0.5 S V at V < 2.7 V
M
CC
CC
and V are the typical output voltage drop that occur with the output load.
OL
OH
V
I
1/f
MAX
PE INPUT
GND
V
M
t
V
I
t
CP INPUT
GND
V
M
SU
SU
t
h
t
h
V
I
CP INPUT
GND
V
t
M
t
PLH
w
t
PHL
V
OH
t
t
SU
SU
t
h
t
h
V
M
V
I
Qn, TC OUTPUT
V
OL
D
INPUT
GND
n
V
M
SY00071
The shaded areas indicate when the input is permitted
to change for predictable output performance.
Waveform 1. Clock (CP) to outputs (Q , TC) propagation
delays, the clock pulse width and the maximum clock
frequency.
n
SC00137
Waveform 4. Setup and hold times for the input (D ) and
n
parallel enable input (PE).
V
I
CET
TC
V
V
M
M
CEP, CET
INPUT
V
t
M
GND
t
t
PLH
PHL
t
t
h
t
su
su
h
V
V
M
M
V
I
V
V
M
CP INPUT
GND
M
SF00792
Waveform 2. Input (CET) to output (TC) propagation delays
and output transition times.
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SC00138
Waveform 5. CEP and CET setup and hold times.
V
V
M
U/D
TC
M
TEST CIRCUIT
t
t
PLH
PHL
S
1
V
V
M
M
2 * V
V
CC
CC
Open
GND
SF00793
500Ω
V
V
O
Waveform 3. Master reset (MR) pulse width, the master reset
I
PULSE
GENERATOR
to output (Q , TC) propagation delays and the master reset to
clock (CP) removal times.
n
D.U.T.
50pF
500Ω
R
T
C
L
SWITCH POSITION
TEST
S
V
V
I
1
CC
t
t
Open
< 2.7V
2.7–3.6V
V
CC
PLH/ PHL
2.7V
SV00903
Waveform 6. Load circuitry for switching times.
9
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
10
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
11
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
12
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
NOTES
13
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down
binary counter
74LVC169
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 05-96
9397-750-04498
Document order number:
Philips
Semiconductors
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74LVC193DB-T
IC LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, Counter
NXP
74LVC193PW
IC LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, Counter
NXP
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