74LVC1G10GW [NXP]
Single 3-input NAND gate; 单3输入与非门
| 型号： | 74LVC1G10GW |
| 厂家： | 
NXP |
| 描述： | Single 3-input NAND gate |
| 文件： | 总14页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G10
Single 3-input NAND gate
Rev. 01 — 2 October 2007
Product data sheet
1. General description
The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8-B/JESD36 (2.7 V to 3.6 V).
■ ±24 mA output drive (VCC = 3.0 V)
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 6 leads SOT457
Version
74LVC1G10GW
74LVC1G10GV
74LVC1G10GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
SC-74
XSON6
SOT363
plastic extremely thin small outline package;
SOT886
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
74LVC1G10GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package;
SOT891
no leads; 6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
74LVC1G10GW
74LVC1G10GV
74LVC1G10GM
74LVC1G10GF
Marking code
YM
YM
YM
YM
5. Functional diagram
1
A
A
3
6
4
B
C
Y
1
3
6
B
C
Y
&
4
001aag688
001aag686
001aag687
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
2 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
6. Pinning information
6.1 Pinning
74LVC1G10
74LVC1G10
A
GND
B
1
2
3
6
5
4
C
74LVC1G10
1
2
3
6
5
4
A
GND
B
C
A
GND
B
1
2
3
6
5
4
C
V
Y
CC
V
Y
CC
V
CC
Y
001aag690
001aag691
Transparent top view
Transparent top view
001aag689
Fig 4. Pin configuration SOT363
and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Pin description
Pin
Symbol
Description
data input
A
1
2
3
4
5
6
GND
B
ground (0 V)
data input
Y
data output
supply voltage
data input
VCC
C
7. Functional description
Table 4.
Function table[1]
Input
Output
A
H
L
B
H
X
L
C
H
X
X
L
Y
L
H
H
H
X
X
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
3 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
−0.5
−0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
°C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
−100
-
[3]
total power dissipation
storage temperature
Tamb = −40 °C to +125 °C
250
+150
−65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
input voltage
output voltage
1.65
-
-
-
-
-
-
-
VI
0
5.5
V
VO
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
+125
20
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
4 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input VCC = 1.65 V to 1.95 V
0.65VCC
-
-
-
-
-
-
-
-
-
0.65VCC
-
V
V
V
V
V
V
V
V
voltage
VCC = 2.3 V to 2.7 V
1.7
-
1.7
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
-
0.7VCC
0.7VCC
VIL
LOW-level input VCC = 1.65 V to 1.95 V
-
-
-
-
0.35VCC
0.7
-
-
-
-
0.35VCC
0.7
voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.8
0.8
0.3VCC
0.3VCC
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −100 µA;
V
CC − 0.1
-
-
VCC − 0.1
-
V
VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 µA;
-
-
0.10
-
0.10
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND;
-
-
-
-
-
-
-
0.45
0.30
0.40
0.55
0.55
±5
-
-
-
-
-
-
0.70
0.45
0.60
0.80
0.80
±100
V
-
V
-
V
-
-
V
V
II
input leakage
current
±0.1
µA
VCC = 0 V to 5.5 V
IOFF
ICC
∆ICC
CI
power-off
leakage current
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
±0.1
0.1
5
±10
10
500
-
-
-
-
-
±200
200
5000
-
µA
µA
µA
pF
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
additional supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 2.3 V to 5.5 V; per pin
input
VCC = 3.3 V;
3
capacitance
VI = GND to VCC
[1] All typical values are measured at Tamb = 25 °C.
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
5 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay A, B and C to Y; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.5
1.0
1.0
1.0
1.0
-
4.7
3.0
3.0
2.6
1.9
12
18.0
6.5
6.0
5.0
3.6
-
1.5
1.0
1.0
1.0
1.0
-
21.5
7.8
7.5
6.2
4.4
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
V
I
A, B, C,
input
V
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
OL
001aag692
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (A, B, C) to output (Y) propagation delays
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
6 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
Table 9.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5VCC
0.5VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuit for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
7 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 9. Package outline SOT363 (SC-88)
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
8 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-11-07
06-03-16
SOT457
SC-74
Fig 10. Package outline SOT457 (SC-74)
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
9 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 11. Package outline SOT886 (XSON6)
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
10 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 12. Package outline SOT891 (XSON6)
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
11 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G10_1
20071002
Product data sheet
-
-
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
12 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
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General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
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changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
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space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G10_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 2 October 2007
13 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 October 2007
Document identifier: 74LVC1G10_1
相关型号：
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