74LVC1G14GM,115 [NXP]
74LVC1G14 - Single Schmitt-trigger inverter SON 6-Pin;
| 型号： | 74LVC1G14GM,115 |
| 厂家： | 
NXP |
| 描述： | 74LVC1G14 - Single Schmitt-trigger inverter SON 6-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G14
Single Schmitt-trigger inverter
Rev. 12 — 6 August 2012
Product data sheet
1. General description
The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the input
makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Input accepts voltages up to 5 V
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Specified from 40 C to +85 C and 40 C to +125 C.
3. Applications
Wave and pulse shaper
Astable multivibrator
Monostable multivibrator
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G14GW
40 C to +125 C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G14GV
74LVC1G14GM
40 C to +125 C
40 C to +125 C
SC-74A
XSON6
plastic surface-mounted package; 5 leads
SOT753
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
74LVC1G14GF
74LVC1G14GN
74LVC1G14GS
74LVC1G14GX
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON6
XSON6
XSON6
X2SON5
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
SOT1202
SOT1226
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
5. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G14GW
74LVC1G14GV
74LVC1G14GM
74LVC1G14GF
74LVC1G14GN
74LVC1G14GS
74LVC1G14GX
VF
V14
VF
VF
VF
VF
VF
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
A
Y
4
2
A
Y
2
4
mna025
mna023
mna024
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
2 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
7. Pinning information
7.1 Pinning
74LVC1G14
74LVC1G14
n.c.
A
1
2
3
6
5
4
V
CC
1
2
3
5
4
n.c.
A
V
Y
CC
n.c.
Y
GND
GND
001aab656
Transparent top view
001aab655
Fig 4. Pin configuration SOT353-1 and SOT753
Fig 5. Pin configuration SOT886
74LVC1G14
74LVC1G14
n.c.
A
1
2
5
4
V
Y
CC
n.c.
A
1
2
3
6
5
4
V
CC
3
GND
n.c.
Y
GND
001aae976
aaa-003024
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7. Pin configuration SOT1226 (X2SON5)
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP5 and X2SON5 XSON6
n.c.
A
1
2
3
4
-
1
2
3
4
5
6
not connected
data input
GND
Y
ground (0 V)
data output
n.c.
VCC
not connected
supply voltage
5
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
3 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
8. Functional description
Table 4.
Function table[1]
Input
Output
A
L
Y
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
0.5
50
-
Max
+6.5
+6.5
VCC + 0.5
+6.5
-
Unit
V
supply voltage
input voltage
output voltage
[1]
[1][2]
[1][2]
V
VO
Active mode
V
Power-down mode
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
mA
mA
C
IOK
IO
VO > VCC or VO < 0 V
VO = 0 V to VCC
50
-
50
ICC
IGND
Tstg
Ptot
supply current
-
+100
-
ground current
100
65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
0
Typ
Max
Unit
supply voltage
input voltage
output voltage
-
-
-
-
-
5.5
V
VI
5.5
V
VO
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
C
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
4 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOH
HIGH-level
VI = VT+ or VT
output voltage
IO = 100 A;
VCC 0.1
-
-
VCC 0.1
-
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VT+ or VT
1.2
1.9
2.2
2.3
3.8
1.54
2.15
2.50
2.62
4.11
-
-
-
-
-
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output voltage
IO = 100 A;
-
-
0.10
-
0.10
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
0.07
0.12
0.17
0.33
0.39
0.1
0.45
0.30
0.40
0.55
0.55
5
-
-
-
-
-
-
0.70
0.45
0.60
0.80
0.80
V
V
V
V
V
II
input leakage VI = 5.5 V or GND;
100 A
current
VCC = 0 V to 5.5 V
IOFF
power-off
leakage
current
VI or VO = 5.5 V; VCC = 0 V
-
0.1
10
-
200 A
ICC
ICC
CI
supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
-
-
0.1
5
10
500
-
-
-
-
200
A
additional
VI = VCC 0.6 V; IO = 0 A;
5000 A
supply current VCC = 2.3 V to 5.5 V
input
VCC = 3.3 V; VI = GND to VCC
5.0
-
pF
capacitance
[1] All typical values are measured at maximum VCC and Tamb = 25 C.
Table 8.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VT+
positive-going
threshold voltage
see Figure 10 and Figure 11
VCC = 1.8 V
0.82
1.03
1.29
1.84
2.19
1.0
1.2
1.5
2.1
2.5
1.14
0.79
1.00
1.26
1.81
2.16
1.14
1.40
1.71
2.36
2.79
V
V
V
V
V
VCC = 2.3 V
1.40
1.71
2.36
2.79
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
5 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
Table 8.
Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VT
negative-going
threshold voltage
see Figure 10 and Figure 11
VCC = 1.8 V
0.46
0.65
0.88
1.32
1.58
0.6
0.8
1.0
1.5
1.8
0.75
0.96
1.24
1.84
2.24
0.46
0.65
0.88
1.32
1.58
0.78
0.99
1.27
1.87
2.27
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
VH
hysteresis voltage (VT+ VT); see Figure 10,
Figure 11 and Figure 12
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.26
0.28
0.31
0.40
0.47
0.4
0.4
0.5
0.6
0.6
0.51
0.57
0.64
0.77
0.88
0.19
0.22
0.25
0.34
0.41
0.51
0.57
0.64
0.77
0.88
V
V
V
V
V
[1] All typical values are measured at Tamb = 25 C
12. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay A to Y; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.7
0.7
0.7
0.7
-
4.1
2.8
3.2
11.0
6.5
6.5
5.5
5.0
-
1.0
0.7
0.7
0.7
0.7
-
14.0
8.5
8.5
7.0
6.5
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
3.0
2.2
15.4
VCC = 4.5 V to 5.5 V
[3]
CPD
power dissipation VCC = 3.3 V; VI = GND to VCC
capacitance
[1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] pd is the same as tPLH and tPHL
t
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V.
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
6 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
13. Waveforms
V
I
V
A input
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
mna640
OL
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The data input (A) to output (Y) propagation delays
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 VCC
0.5 VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
EXT = External voltage for measuring switching times.
V
Fig 9. Test circuit for measuring switching times
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
7 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
open
open
open
open
open
500
500
500
500
3.0 V to 3.6 V
4.5 V to 5.5 V
14. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT limits at 70 % and 20 %.
Fig 10. Transfer characteristic
Fig 11. Definition of VT+, VT and VH
mna641
10
I
CC
(mA)
8
6
4
2
0
0
1
2
3
V (V)
I
VCC = 3.0 V.
Fig 12. Typical transfer characteristics
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
8 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where:
Padd = additional power dissipation (W);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LVC1G14 is shown in Figure 14.
mna642
12
average
I
CC
10
(mA)
positive-going
edge
8
6
4
negative-going
edge
2
0
0
2
4
6
V
CC
(V)
Linear change of VI between 0.8 V to 2.0 V.
All values given are typical unless otherwise specified.
Fig 13. Average additional supply current as a function of supply voltage
R
C
mna035
1
T
1
-- ---------------------
f =
0.5 RC
Fig 14. Relaxation oscillator
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
9 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
16. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 15. Package outline SOT353-1 (TSSOP5)
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
10 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 16. Package outline SOT753 (SC-74A)
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
11 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
1
e
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
L
L
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.20 1.45 1.00 0.6 0.5 0.30 0.35
0.17 1.40 0.95 0.27 0.32
mm nom
min
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig 17. Package outline SOT886 (XSON6)
74LVC1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 6 August 2012
12 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(1)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 18. Package outline SOT891 (XSON6)
74LVC1G14
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Product data sheet
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NXP Semiconductors
Single Schmitt-trigger inverter
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig 19. Package outline SOT1115 (XSON6)
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
14 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig 20. Package outline SOT1202 (XSON6)
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
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74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.35 mm
SOT1226
D
A
B
X
A
E
A
1
A
3
detail X
terminal 1
index area
e
C
v
C
C
A
B
b
y
1
y
C
w
1
2
terminal 1
index area
3
L
5
4
0
1 mm
scale
v
Dimensions
Unit
max 0.35 0.04 0.128 0.85 0.30 0.85 0.27
(1)
A
A
1
A
3
D
D
E
b
e
k
L
w
y
y
1
h
0.27
0.22 0.1 0.05 0.05 0.05
0.20 0.17
mm nom
min
0.80 0.25 0.80 0.22 0.48
0.040 0.75 0.20 0.75 0.17
Note
1. Dimension A is including plating thickness.
2. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1226_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
EIAJ
12-04-10
12-04-25
SOT1226
Fig 21. Package outline SOT1226 (X2SON5)
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
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NXP Semiconductors
Single Schmitt-trigger inverter
17. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
18. Revision history
Table 13. Revision history
Document ID
74LVC1G14 v.12
Modifications:
74LVC1G14 v.11
Modifications:
Release date
20120806
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G14 v.11
• Package outline drawing of SOT1226 (Figure 21) modified.
20120412 Product data sheet
-
74LVC1G14 v.10
74LVC1G14 v.9
• Added type number 74LVC1G14GX (SOT1226)
• Package outline drawing of SOT886 (Figure 17) modified.
74LVC1G14 v.10
Modifications:
20111206
Product data sheet
-
• Legal pages updated.
74LVC1G14 v.9
74LVC1G14 v.8
74LVC1G14 v.7
74LVC1G14 v.6
74LVC1G14 v.5
74LVC1G14 v.4
74LVC1G14 v.3
74LVC1G14 v.2
74LVC1G14 v.1
20110922
20101110
20070718
20060615
20040910
20021119
20020521
20010406
20001212
Product data sheet
-
-
-
-
-
-
-
-
-
74LVC1G14 v.8
74LVC1G14 v.7
74LVC1G14 v.6
74LVC1G14 v.5
74LVC1G14 v.4
74LVC1G14 v.3
74LVC1G14 v.2
74LVC1G14 v.1
-
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
Product specification
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
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Single Schmitt-trigger inverter
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
18 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G14
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Product data sheet
Rev. 12 — 6 August 2012
19 of 20
74LVC1G14
NXP Semiconductors
Single Schmitt-trigger inverter
21. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics. . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
13
14
15
16
17
18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2012
Document identifier: 74LVC1G14
相关型号：
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