74LVC1G57GM,132 [NXP]

74LVC1G57 - Low-power configurable multiple function gate SON 6-Pin;
74LVC1G57GM,132
型号: 74LVC1G57GM,132
厂家: NXP    NXP
描述:

74LVC1G57 - Low-power configurable multiple function gate SON 6-Pin

光电二极管 逻辑集成电路
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74LVC1G57  
Low-power configurable multiple function gate  
Rev. 03 — 19 July 2007  
Product data sheet  
1. General description  
The 74LVC1G57 provides configurable multiple functions. The output state is determined  
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,  
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
All inputs (A, B and C) have Schmitt trigger action. They are capable of transforming  
slowly changing input signals into sharply defined, jitter-free output signals.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range  
40 °C to +125 °C  
40 °C to +125 °C  
40 °C to +125 °C  
Name  
SC-88  
SC-74  
XSON6  
Description  
plastic surface-mounted package; 6 leads  
Version  
74LVC1G57GW  
74LVC1G57GV  
74LVC1G57GM  
SOT363  
plastic surface-mounted package (TSOP6); 6 leads SOT457  
plastic extremely thin small outline package;  
SOT886  
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm  
74LVC1G57GF  
40 °C to +125 °C  
XSON6  
plastic extremely thin small outline package;  
SOT891  
no leads; 6 terminals; body 1 × 1 × 0.5 mm  
4. Marking  
Table 2.  
Marking  
Type number  
74LVC1G57GW  
74LVC1G57GV  
74LVC1G57GM  
74LVC1G57GF  
Marking code  
YC  
V57  
YC  
YC  
5. Functional diagram  
3
1
6
A
B
C
4
Y
001aab583  
Fig 1. Logic symbol  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
2 of 17  
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
6. Pinning information  
6.1 Pinning  
74LVC1G57  
74LVC1G57  
B
GND  
A
1
2
3
6
5
4
C
74LVC1G157  
1
2
3
6
5
4
B
GND  
A
C
B
GND  
A
1
2
3
6
5
4
C
V
Y
CC  
V
Y
CC  
V
CC  
Y
001aaf139  
001aaf140  
Transparent top view  
Transparent top view  
001aaf138  
Fig 2. Pin configuration SOT363  
(SC-88) and SOT457 (SC-74)  
Fig 3. Pin configuration SOT886  
(XSON6)  
Fig 4. Pin configuration SOT891  
(XSON6)  
6.2 Pin description  
Table 3.  
Pin description  
Pin  
Symbol  
Description  
data input  
B
1
2
3
4
5
6
GND  
A
ground (0 V)  
data input  
Y
data output  
supply voltage  
data input  
VCC  
C
7. Functional description  
Table 4.  
Function table[1]  
Input  
Output  
C
L
B
L
A
L
Y
H
L
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
[1] H = HIGH voltage level;  
L = LOW voltage level.  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
3 of 17  
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
7.1 Logic configurations  
Table 5.  
Function selection table  
Logic function  
Figure  
2-input AND  
see Figure 5  
2-input AND with both inputs inverted  
2-input NAND with inverted input  
2-input OR with inverted input  
2-input NOR  
see Figure 8  
see Figure 6 and Figure 7  
see Figure 6 and Figure 7  
see Figure 8  
2-input NOR with both inputs inverted  
2-input XNOR  
see Figure 5  
see Figure 9  
Inverter  
see Figure 10  
Buffer  
see Figure 11  
V
CC  
V
CC  
B
C
B
Y
C
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
C
B
Y
C
Y
001aab585  
001aab584  
Fig 5. 2-input AND gate or 2-input NOR gate with both  
inputs inverted  
Fig 6. 2-input NAND gate with input B inverted or  
2-input OR gate with inverted C input  
V
CC  
V
CC  
A
C
Y
Y
A
C
1
2
3
6
5
4
C
Y
Y
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab587  
001aab586  
Fig 7. 2-input NAND gate with input C inverted or  
2-input OR gate with inverted A input  
Fig 8. 2-input NOR gate or 2-input AND gate with both  
inputs inverted  
V
CC  
V
CC  
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
Y
A
Y
A
Y
001aab588  
001aab589  
Fig 9. 2-input XNOR gate  
Fig 10. Inverter  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
4 of 17  
 
 
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
V
CC  
B
1
2
3
6
5
4
B
Y
Y
001aab590  
Fig 11. Buffer  
8. Limiting values  
Table 6.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
50  
0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
VI  
+6.5  
±50  
+6.5  
+6.5  
±50  
+100  
-
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
Active mode  
mA  
V
[1][2]  
[1][2]  
VO  
0.5  
0.5  
-
Power-down mode  
VO = 0 V to VCC  
V
IO  
output current  
mA  
mA  
mA  
°C  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
250  
[3]  
Tamb = 40 °C to +125 °C  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
[3] For SC-88 and SC-74 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.  
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.  
9. Recommended operating conditions  
Table 7.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
1.65  
0
Typ  
Max  
5.5  
Unit  
supply voltage  
input voltage  
output voltage  
-
-
-
-
-
V
VI  
5.5  
V
VO  
Active mode  
0
VCC  
5.5  
V
VCC = 0 V; Power-down mode  
0
V
Tamb  
ambient temperature  
40  
+125  
°C  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
5 of 17  
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
10. Static characteristics  
Table 8.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 °C to +85 °C  
40 °C to +125 °C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
VOL  
LOW-level  
VI = VCC or GND  
output voltage  
IO = 100 µA;  
-
-
0.1  
-
0.1  
V
VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = VCC or GND  
-
-
-
-
-
-
-
-
-
-
0.45  
0.3  
-
-
-
-
-
0.7  
0.45  
0.6  
V
V
V
V
V
0.4  
0.55  
0.55  
0.8  
0.8  
VOH  
HIGH-level  
output voltage  
IO = 100 µA;  
VCC 0.1  
-
-
V
CC 0.1  
-
V
VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
1.2  
1.9  
2.2  
2.3  
3.8  
-
-
-
-
0.95  
1.7  
1.9  
2.0  
3.4  
-
-
V
-
-
V
-
-
-
V
-
-
-
-
-
V
-
V
II  
input leakage VI = 5.5 V or GND;  
±0.1  
±5  
±100  
µA  
current  
VCC = 0 V to 5.5 V  
IOFF  
power-off  
leakage  
current  
VI or VO = 5.5 V; VCC = 0 V  
-
±0.1  
±10  
-
±200  
µA  
µA  
ICC  
ICC  
CI  
supply current VI = 5.5 V or GND; IO = 0 A;  
CC = 1.65 V to 5.5 V  
-
-
-
0.1  
5
10  
500  
-
-
-
-
200  
V
additional  
supply current  
VI = VCC 0.6 V; IO = 0 A;  
VCC = 2.3 V to 5.5 V  
5000 µA  
pF  
input  
2.5  
-
capacitance  
[1] Typical values are measured at maximum VCC and Tamb = 25 °C.  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
6 of 17  
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
11. Dynamic characteristics  
Table 9.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 13.  
Symbol Parameter Conditions 40 °C to +85 °C  
40 °C to +125 °C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
tpd  
propagation delay A, B, C to Y; see Figure 12  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
1.0  
0.5  
0.5  
0.5  
0.5  
-
6.0  
3.5  
4.2  
3.8  
3.0  
22  
14.4  
8.3  
8.5  
6.3  
5.1  
-
1.0  
0.5  
0.5  
0.5  
0.5  
-
18  
10.4  
10.6  
7.9  
6.4  
-
ns  
ns  
ns  
ns  
ns  
pF  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
[3]  
CPD  
power dissipation VCC = 3.3 V; VI = GND to VCC  
capacitance  
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.  
[2] tpd is the same as tPLH and tPHL  
[3] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of outputs.  
12. Waveforms  
V
I
A, B, C input  
GND  
V
V
M
M
t
t
PLH  
PHL  
V
OH  
V
V
V
M
Y output  
M
V
OL  
t
t
PLH  
PHL  
V
OH  
Y output  
V
M
M
V
OL  
001aab593  
Measurement points are given in Table 10.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 12. Input A, B and C to output Y propagation delay times  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
7 of 17  
 
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
Table 10. Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
VI  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5VCC  
0.5VCC  
1.5 V  
1.5 V  
0.5VCC  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
0.5VCC  
0.5VCC  
1.5 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
0.5VCC  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Measurement points are given in Table 11.  
Definitions test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 13. Load circuit for switching times  
Table 11. Measurement points  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr = tf  
RL  
tPLH, tPHL  
open  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
open  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
open  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
8 of 17  
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
13. Transfer characteristics  
Table 12. Transfer characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 °C to +85 °C  
Min Max  
Typ[1]  
40 °C to +125 °C Unit  
Min Max  
VT+  
VT−  
VH  
positive-going  
threshold voltage Figure 16 and Figure 17  
see Figure 14, Figure 15,  
VCC = 1.8 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
VCC = 5.5 V  
0.70  
1.11  
1.50  
2.16  
2.61  
1.02  
1.20  
1.60  
2.00  
2.74  
3.33  
0.67  
1.20  
V
V
V
V
V
1.42  
1.79  
2.52  
2.99  
1.08  
1.47  
2.13  
2.58  
1.60  
2.00  
2.74  
3.33  
negative-going  
threshold voltage Figure 16 and Figure 17  
see Figure 14, Figure 15,  
VCC = 1.8 V  
VCC = 2.3 V  
0.30  
0.58  
0.80  
1.21  
1.45  
0.53  
0.77  
1.04  
1.55  
1.86  
0.72  
1.00  
1.30  
1.90  
2.29  
0.30  
0.58  
0.80  
1.21  
1.45  
0.75  
1.03  
1.33  
1.93  
2.32  
V
V
V
V
V
VCC = 3.0 V  
VCC = 4.5 V  
VCC = 5.5 V  
hysteresis voltage see Figure 14, Figure 15,  
(VT+ VT)  
Figure 16 and Figure 17  
VCC = 1.8 V  
0.30  
0.40  
0.50  
0.71  
0.71  
0.48  
0.64  
0.75  
0.97  
1.13  
0.62  
0.80  
1.00  
1.20  
1.40  
0.23  
0.34  
0.44  
0.65  
0.65  
0.62  
0.80  
1.00  
1.20  
1.40  
V
V
V
V
V
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
VCC = 5.5 V  
[1] Typical values are measured at Tamb = 25 °C.  
14. Waveforms transfer characteristics  
V
O
V
T+  
V
I
V
H
V
T−  
V
I
V
V
O
H
V
V
T+  
T−  
mna207  
mna208  
VT+ and VTlimits are at 70 % and 20 %.  
Fig 14. Transfer characteristic  
Fig 15. Definition of VT+, VTand VH  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
9 of 17  
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
V
O
V
T+  
V
I
V
H
V
T−  
V
O
V
I
V
H
V
V
T+  
T−  
mnb155  
mnb154  
VT+ and VTlimits are at 70 % and 20 %.  
Fig 16. Transfer characteristic  
Fig 17. Definition of VT+, VTand VH  
001aab594  
16  
I
CC  
(mA)  
12  
8
4
0
0
1
2
3
V (V)  
I
Fig 18. Typical 74LVC1G57 transfer characteristic; VCC = 3.0 V  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
10 of 17  
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
15. Package outline  
Plastic surface-mounted package; 6 leads  
SOT363  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B  
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
UNIT  
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max  
0.30  
0.20  
1.1  
0.8  
0.25  
0.10  
2.2  
1.8  
1.35  
1.15  
2.2  
2.0  
0.45  
0.15  
0.25  
0.15  
mm  
0.1  
1.3  
0.65  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
04-11-08  
06-03-16  
SOT363  
SC-88  
Fig 19. Package outline SOT363 (SC-88)  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
11 of 17  
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
Plastic surface-mounted package (TSOP6); 6 leads  
SOT457  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
c
1
2
3
L
p
e
b
p
w
M B  
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
05-11-07  
06-03-16  
SOT457  
SC-74  
Fig 20. Package outline SOT457 (SC-74)  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
12 of 17  
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm  
SOT886  
b
1
2
3
4×  
(2)  
L
L
1
e
6
5
4
e
1
e
1
6×  
(2)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.25  
0.17  
1.5  
1.4  
1.05  
0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.6  
0.5  
Notes  
1. Including plating thickness.  
2. Can be visible in some manufacturing processes.  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
04-07-15  
04-07-22  
SOT886  
MO-252  
Fig 21. Package outline SOT886 (XSON6)  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
13 of 17  
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm  
SOT891  
b
1
2
3
4×  
(1)  
L
L
1
e
6
5
4
e
1
e
1
6×  
(1)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.20 1.05 1.05  
0.12 0.95 0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.55 0.35  
Note  
1. Can be visible in some manufacturing processes.  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
05-04-06  
07-05-15  
SOT891  
Fig 22. Package outline SOT891 (XSON6)  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
14 of 17  
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
16. Abbreviations  
Table 13. Abbreviations  
Acronym  
CMOS  
TTL  
Description  
Complementary Metal Oxide Semiconductor  
Transistor-Transistor Logic  
Human Body Model  
HBM  
ESD  
ElectroStatic Discharge  
Machine Model  
MM  
DUT  
Device Under Test  
17. Revision history  
Table 14. Revision history  
Document ID  
74LVC1G57_3  
Modifications:  
Release date  
20070719  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74LVC1G57_2  
The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
Legal texts have been adapted to the new company name where appropriate.  
Section 10 “Static characteristics”:  
Changed: Conditions for input leakage current and supply current.  
New package outline drawing for XSON6/SOT891.  
74LVC1G57_2  
74LVC1G57_1  
20060911  
20040906  
Product data sheet  
Product data sheet  
-
-
74LVC1G57_1  
-
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
15 of 17  
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
18. Legal information  
18.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of a NXP Semiconductors product can reasonably be expected to  
18.2 Definitions  
result in personal injury, death or severe property or environmental damage.  
NXP Semiconductors accepts no liability for inclusion and/or use of NXP  
Semiconductors products in such equipment or applications and therefore  
such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
18.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
18.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
19. Contact information  
For additional information, please visit: http://www.nxp.com  
For sales office addresses, send an email to: salesaddresses@nxp.com  
74LVC1G57_3  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 19 July 2007  
16 of 17  
 
 
 
 
 
 
74LVC1G57  
NXP Semiconductors  
Low-power configurable multiple function gate  
20. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
7.1  
8
Functional description . . . . . . . . . . . . . . . . . . . 3  
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Transfer characteristics. . . . . . . . . . . . . . . . . . . 9  
Waveforms transfer characteristics. . . . . . . . . 9  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
18.1  
18.2  
18.3  
18.4  
19  
20  
Contact information. . . . . . . . . . . . . . . . . . . . . 16  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2007.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 19 July 2007  
Document identifier: 74LVC1G57_3  
 

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