74LVC1G79 [NXP]
Single D-type flip-flop; positive-edge trigger; 单一的D- FL型IP- FL操作;正边沿触发
| 型号： | 74LVC1G79 |
| 厂家： | 
NXP |
| 描述： | Single D-type flip-flop; positive-edge trigger |
| 文件： | 总18页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G79
Single D-type flip-flop;
positive-edge trigger
Product specification
2004 Sep 10
Supersedes data of 2004 Mar 17
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 V to 5.5 V
• High noise immunity
The 74LVC1G79 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
Inputs can be driven from either 3.3 V or 5 V devices.
This feature allows the use of this device in a mixed
3.3 V and 5 V environment.
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• ESD protection:
This device is fully specified for partial Power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
The 74LVC1G79 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
on the LOW-to-HIGH transition of the clock pulse.
The D input must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
• Specified from −40 °C to +85 °C and
−40 °C to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
propagation delay CP to Q
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
3.6
2.3
2.6
2.2
1.7
450
5
ns
ns
ns
ns
ns
V
CC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
fmax
CI
maximum frequency
input capacitance
MHz
pF
CPD
power dissipation capacitance
per buffer
VCC = 3.3 V; notes 1 and 2
17
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2004 Sep 10
2
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
CP
D
Q
↑
↑
L
L
H
X
L
H
q
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
PACKAGE MATERIAL
TYPE NUMBER
TEMPERATURE
PINS
CODE
MARKING
RANGE
74LVC1G79GW
74LVC1G79GV
74LVC1G79GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
5
5
6
SC-88A
SC-74A
XSON6
plastic
plastic
plastic
SOT353
SOT753
SOT886
VP
V79
VP
PINNING
PIN SC-88A; SC-74A
PIN XSON6
SYMBOL
DESCRIPTION
1
2
3
4
-
1
2
3
4
5
6
D
data input D
CP
clock pulse input CP
ground (0 V)
GND
Q
data output Q
not connected
supply voltage
n.c.
VCC
5
2004 Sep 10
3
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
79
D
CP
1
2
3
6
5
4
V
CC
1
2
3
5
4
D
CP
V
CC
79
n.c.
Q
GND
Q
GND
001aab660
001aab661
Transparent top view
Fig.1 Pin configuration TSSOP5 and VSSOP5.
Fig.2 Pin configuration XSON6.
handbook, halfpage
1
2
4
1
2
D
Q
4
D
CP
mna441
CP
MNA440
Fig.3 Logic symbol.
Fig.4 IEE/IEC logic symbol.
2004 Sep 10
4
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
C
TG
C
MNA442
Fig.5 Logic diagram.
2004 Sep 10
5
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
VCC
VI
V
input voltage
0
5.5
VCC
5.5
+125
20
V
VO
output voltage
active mode
0
V
VCC = 0 V; Power-down mode
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0 V
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
active mode; note 1
Power-down mode; note 1
VO = 0 V to VCC
mA
V
−0.5
−0.5
−
VCC + 0.5
+6.5
±50
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
250
−65
−
Ptot
Tamb = −40 °C to +125 °C
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2004 Sep 10
6
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
HIGH-level input voltage
LOW-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.45
0.3
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
0.4
3.0
0.55
0.55
4.5
VOH
HIGH-level output
voltage
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
V
1.2
1.9
2.2
2.3
3.8
−
−
V
−
V
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
VI or VO = 5.5 V
±0.1
±0.1
±5
±10
µA
µA
Ioff
power OFF leakage
current
0
−
ICC
quiescent supply current VI = VCC or GND; 5.5
IO = 0 A
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent
VI = VCC − 0.6 V;
2.3 to 5.5
500
supply current per input IO = 0 A
pin
2004 Sep 10
7
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
LOW-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.70
0.45
0.60
0.80
0.80
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
3.0
4.5
VOH
HIGH-level output
voltage
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
V
0.95
1.7
1.9
2.0
3.4
−
−
V
−
V
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
VI or VO = 5.5 V
±100
±200
µA
µA
Ioff
power OFF leakage
current
0
−
ICC
quiescent supply current VI = VCC or GND; 5.5
IO = 0 A
−
−
−
−
200
µA
µA
∆ICC
additional quiescent
VI = VCC − 0.6 V;
2.3 to 5.5
5000
supply current per input IO = 0 A
pin
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Sep 10
8
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
AC CHARACTERISTICS
GND = 0 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH propagation delay
CP to Q
see Figs 6 and 8 1.65 to 1.95 1.0
3.6
2.3
2.6
2.2
1.7
1.4
0.9
0.9
0.6
0.6
9.9
ns
2.3 to 2.7
2.7
0.5
0.5
0.5
0.5
7.0
6.0
5.0
3.8
−
ns
ns
3.0 to 3.6
4.5 to 5.5
ns
ns
tsu
set-up time D to CP
hold time D to CP
see Figs 7 and 8 1.65 to 1.95 2.5
ns
2.3 to 2.7
1.7
1.7
1.3
1.2
0
−
ns
2.7
−
ns
3.0 to 3.6
−
ns
4.5 to 5.5
−
ns
th
see Figs 7 and 8 1.65 to 1.95
−0.7
−0.4
−0.3
−0.3
−0.2
1.1
−
ns
2.3 to 2.7
2.7
0
−
ns
+0.5
+0.5
+0.5
−
ns
3.0 to 3.6
4.5 to 5.5
−
ns
−
ns
tW
clock pulse width HIGH
or LOW
see Figs 7 and 8 1.65 to 1.95 3.0
−
ns
2.3 to 2.7
2.7
2.5
2.5
2.5
2.0
0.7
−
ns
0.6
−
ns
3.0 to 3.6
4.5 to 5.5
0.6
−
ns
0.5
−
ns
fmax
maximum clock pulse
frequency
see Figs 7 and 8 1.65 to 1.95 160
250
300
350
450
500
−
MHz
MHz
MHz
MHz
MHz
2.3 to 2.7
2.7
160
160
160
200
−
−
3.0 to 3.6
4.5 to 5.5
−
−
2004 Sep 10
9
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +125 °C
tPHL/tPLH propagation delay
CP to Q
see Figs 6 and 8 1.65 to 1.95 1.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
12.5
ns
2.3 to 2.7
2.7
0.5
0.5
0.5
0.5
9.0
8.0
6.5
5.0
−
ns
ns
3.0 to 3.6
4.5 to 5.5
ns
ns
tsu
set-up time D to CP
hold time D to CP
see Figs 7 and 8 1.65 to 1.95 2.5
ns
2.3 to 2.7
1.7
1.7
1.2
1.2
0
−
ns
2.7
−
ns
3.0 to 3.6
−
ns
4.5 to 5.5
−
ns
th
see Figs 7 and 8 1.65 to 1.95
−
ns
2.3 to 2.7
2.7
0
−
ns
0.5
0.5
0.5
−
ns
3.0 to 3.6
4.5 to 5.5
−
ns
−
ns
tW
clock pulse width
HIGH or LOW
see Figs 7 and 8 1.65 to 1.95 3.0
−
ns
2.3 to 2.7
2.7
2.5
2.5
2.5
2.0
−
ns
−
ns
3.0 to 3.6
4.5 to 5.5
−
ns
−
ns
fmax
maximum clock pulse
frequency
see Figs 7 and 8 1.65 to 1.95 160
−
MHz
MHz
MHz
MHz
MHz
2.3 to 2.7
2.7
160
160
160
200
−
−
3.0 to 3.6
4.5 to 5.5
−
−
Note
1. All typical values are measured at Tamb = 25 °C.
2004 Sep 10
10
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
AC WAVEFORMS
V
I
D input
GND
V
I
CP input
V
V
M
M
GND
t
t
PLH
PHL
V
OH
V
V
M
Q output
M
V
MNA443
OL
INPUT
VCC
VM
VI
tr = tf
≤ 2.0 ns
1.65 V to 1.95 V 0.5 × VCC
VCC
2.3 V to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5 × VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 Clock (CP) to output (Q) propagation delay times.
2004 Sep 10
11
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Q output
M
V
MNA647
OL
INPUT
VCC
VM
VI
tr = tf
≤ 2.0 ns
1.65 V to 1.95 V 0.5 × VCC
VCC
2.3 V to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5 × VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Clock (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up times, the CP to D hold
times and maximum clock pulse frequency.
2004 Sep 10
12
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
VCC
VI
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 V to 1.95 V VCC
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2004 Sep 10
13
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
PACKAGE OUTLINES
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
2004 Sep 10
14
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
1
b
c
D
E
e
H
L
Q
v
w
y
p
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
SOT753
SC-74A
02-04-16
2004 Sep 10
15
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
2004 Sep 10
16
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G79
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Sep 10
17
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/05/pp18
Date of release: 2004 Sep 10
Document order number: 9397 750 13766
相关型号：
74LVC1G79GN
LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6
NXP
74LVC1G79GS
LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, 0.35 MM PITCH, SOT-1202, SON-6
NXP
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