74LVC2373APWDH [NXP]
IC LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver;
| 型号： | 74LVC2373APWDH |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver 锁存器 电阻器 |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs; damping resistor
(3-State)
Product specification
IC24 Data Handbook
1997 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
74LVC2373A
74LVCH2373A
FEATURES
DESCRIPTION
The 74LVC2373A/74LVCH2373A is a high performance, low-power,
low-voltage Si-gate CMOS device and superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. This feature allows the use of these devices as
translators in a mixed 3.3V/5V environment.
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• High impedance when V = 0V
The 74LVC2373A/74LVCH2373A is an octal D-type transparent
latch featuring separate D-type inputs for each latch and 3-State
outputs for bus oriented applications. A latch enable (LE) input and
an output enable (OE) input are common to all internal latches.
CC
• Bushold on all data inputs (74LVCH2373A only)
• Integrated 30W damping resistor
The ‘2373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
Dn to Qn
LE to Qn
C = 50pF
L
V
CC
= 3.3V
4.4
5.0
t
/t
ns
PHL PLH
C
C
Input capacitance
5.0
20
pF
pF
I
Power dissipation capacitance per latch
Notes 1, 2
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )Σ (C × V
× f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
Σ (C × V
× f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC.
ORDERING AND PACKAGE INFORMATION
OUTSIDE NORTH
AMERICA
PACKAGES
TEMPERATURE RANGE
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC2373A D
74LVC2373A DB
74LVC2373A PW
74LVCH2373A D
74LVCH2373A DB
74LVCH2373A PW
74LVC2373A D
74LVC2373A DB
LVC2373APW DH
74LVCH2373A D
7LVCH2373A DB
VCH2373APW DH
SOT163-1
SOT339-1
SOT360-1
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
2
1997 Mar 12
853–1940 17843
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
PIN CONFIGURATION
LOGIC SYMBOL
11
LE
1
20
19
V
OE
CC
2
3
4
5
6
7
8
9
Q7
D7
Q0
D0
D1
Q1
Q2
D2
D3
Q3
3
4
D0
D1
D2
D3
D4
D5
D6
D7
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
18
5
17 D6
6
7
16
15
Q6
Q5
8
9
12
15
16
19
13
14
17
18
14 D5
13
12
D4
Q4
OE
GND 10
11 LE
1
SV00657
SV00658
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
PIN NUMBER SYMBOL
FUNCTION
3
4
7
8
D0
D1
D2
D3
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
OE
Output enable input (active LOW)
3-State latch outputs
5
2, 5, 6, 9, 12,
15, 16, 19
Q0–Q7
6
3, 4, 7, 8, 13,
14, 17, 18
D0–D7
Data inputs
9
LATCH
1 to 8
3–STATE
OUTPUTS
12
13
14
17
18
D4
D5
D6
D7
10
11
20
GND
LE
Ground (0V)
15
16
19
Latch enable input (active HIGH)
Positive supply voltage
V
CC
LOGIC SYMBOL (IEEE/IEC)
11
1
LE
11
C1
1
OE
EN1
SV00660
3
2
1D
FUNCTION TABLE
4
7
5
INPUTS
LE
OUTPUTS
Q0 to Q7
OPERATING
INTERNAL
LATCHES
6
MODES
OE
Dn
8
9
Enable and
read register
(transparent
mode)
L
L
H
H
L
H
L
H
L
H
12
13
14
17
18
15
16
19
Latch and read
register
L
L
L
L
I
h
L
H
L
H
Latch register
and disable
outputs
H
H
L
L
I
h
L
H
Z
Z
SV00659
H = HIGH voltage level
h
=
HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L
I
=
=
LOW voltage level
LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
X
Z
=
=
Don’t care
High impedance OFF-state
3
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00661
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.6
V
V
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
2.7
1.2
0
V
V
CC
3.6
CC
V
I
5.5
V
V
DC input voltage range for I/Os
0
V
V
I/O
CC
CC
V
DC output voltage range
0
V
V
O
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +6.5
–50
DC input diode current
V t0
mA
V
I
V
I
DC input voltage
Note 2
–0.5 to +5.5
V
DC input voltage range for I/Os
DC output diode current
–0.5 to V +0.5
V
I/O
OK
CC
I
V
uV or V t 0
±50
mA
V
O
CC
O
V
V
DC output voltage; output HIGH or LOW
DC output voltage; output 3-State
DC output source or sink current
Note 2
Note 2
–0.5 to V +0.5
OUT
OUT
OUT
CC
–0.5 to +6.5
±50
V
I
V
O
= 0 to V
mA
mA
°C
CC
I
, I
DC V or GND current
±100
GND CC
CC
T
stg
Storage temperature range
–60 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 3.0V; V = V or V ; I = –100µA
V
V
V
V
V
V
*0.2
V
V
I
IH
IL
O
CC
CC
CC
CC
CC
CC
CC
= 3.0V; V = V or V I
= –12mA
I = –24mA
*0.6
*1.0
*0.5
*0.2
*0.8
V
HIGH level output voltage
V
I
IH
IL; O
OH
OH
= 3.0V; V = V or V
IL; O
I
IH
7
= 2.7V; V = V or V ; I = –6mA
I
IH
IL
O
7
= 3.0V; V = V or V ; I = –100µA
V
HIGH level output voltage
LOW level output voltage
LOW level output voltage
V
V
V
I
IH
IL
O
CC
7
= 3.0V; V = V or V
I = –12mA
IL; O
I
IH
= 3.0V; V = V or V ; I = 100µA
GND
GND
0.20
0.55
0.40
0.20
0.55
±5
I
IH
IL
O
V
V
OL
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
7
= 2.7V; V = V or V ; I = 6mA
I
IH
IL
O
7
= 3.0V; V = V or V ; I = 100µA
I
IH
IL
O
OL
7
= 3.0V; V = V or V
I = 12mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND Not for I/O pins
±0.1
±0.1
0.1
µA
µA
µA
µA
I
I
I
/I
Input current for common I/O pins
3-State output OFF-state current
Quiescent supply current
= 3.6V; V = V or GND
±15
±10
20
IHZ ILZ
I
CC
I
= 3.6V; V = V or V ; V = V or GND
I IH IL O CC
OZ
CC
I
= 3.6V; V = V or GND; I = 0
0.1
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
2, 3, 4
I
Bushold LOW sustaining current
V
CC
V
CC
V
CC
V
CC
= 3.0V; V =0.8V
75
–
–
–
–
–
–
–
–
µA
µA
µA
µA
BHL
I
2, 3, 4
I
Bushold HIGH sustaining current
= 3.0V; V =2.0V
–75
500
BHH
I
2, 3, 5
I
Bushold LOW overdrive current
= 3.6V
= 3.6V
BHLO
2, 3, 5
I
Bushold HIGH overdrive current
–500
BHHO
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. Valid for data inputs of bushold parts (LVCH-A) only.
3. For data inputs only, control inputs do not have a bushold circuit.
4. The specified sustaining current at the data inputs do not have a bushold circuit.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6. For bushold parts, the bushold circuit is switched off when V exceeds V allowing 5.5V on the input terminal.
I
CC
7. For data outputs of damping resistor parts only.
5
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF
r
f
L
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
V = 1.2V
CC
UNIT
1
MIN
TYP
MAX
MIN
MAX
TYP
Propagation delay
Dn to Qn
t
/t
Figures 1, 5
Figures 2, 5
Figures 3, 5
1.5
1.5
1.5
–
8.5
9.5
9.0
1.5
9.5
11
–
–
–
ns
ns
ns
PHL PLH
Propagation delay
LE to Qn
t
t
t
t
–
–
1.5
1.5
PHL/ PLH
3-State output enable time
OE to Qn
/t
11
PZH PZL
3-State output disble time
OE to Qn
/t
Figures 3, 5
Figure 2
1.5
4.0
2.0
–
–
–
6.0
–
1.5
4.0
3.0
6.5
–
–
–
–
ns
ns
ns
PHZ PLZ
t
LE pulse width HIGH
W
Set-up time
Dn to LE
t
Figure 4
–
–
su
Hold time
Dn to LE
t
h
Figure 4
2.0
–
–
3.0
–
–
ns
NOTE:
1. These typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC WAVEFORMS
V
V
V
V
V
V
V
= 1.5 V at V w 2.7 V
M
CC
= 0.5 S V at V < 2.7 V
M
CC
CC
and V are the typical output voltage drop that occur with the output load.
OL
OH
= V + 0.3 V at V ≥ 2.7 V
X
X
Y
Y
OL
CC
– V + 0.1
V at V < 2.7 V
CC CC
OL
= V – 0.3 V at V ≥ 2.7 V
OH
CC
= V – 0.1
V at V < 2.7 V
CC CC
OH
V
I
V
I
LE INPUT
GND
V
M
INPUTS
GND
V
M
t
W
t
t
PLH
PHL
t
t
PLH
PHL
V
OH
V
OH
OUTPUTS
Q OUTPUT
n
V
V
M
M
V
OL
V
OL
SV00690
SV00691
Figure 1. nput (Dn) to output (Qn) propagation delays
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Qn) propagation delays
6
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
TEST CIRCUIT
V
I
S
1
V
2 < V
Open
GND
OE INPUT
GND
M
CC
V
CC
500Ω
500Ω
t
t
PZL
PLZ
V
V
O
I
PULSE
GENERATOR
V
D.U.T.
CC
OUTPUT
LOW–to–OFF
OFF–to–LOW
V
M
50pF
C
L
R
T
V
X
V
OL
t
PZH
t
PHZ
Test
/t
S
1
V
OH
V
V
V
CC
I
Y
t
Open
OUTPUT
HIGH–to–OFF
OFF–to–HIGH
PLH PHL
V
M
t 2.7V
2.7V – 3.6V
V
t
/t
2 < V
CC
CC
PLZ PZL
2.7V
t
/t
GND
GND
PHZ PZH
outputs
disabled
outputs
enabled
outputs
enabled
SY00003
Figure 5. Load circuitry for switching times
SV00692
Figure 3. 3-State enable and disable times
V
I
D
INPUT
V
n
M
GND
t
h
t
h
t
su
t
su
V
I
LE INPUT
GND
V
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00693
Figure 4. Data set-up and hold times
for the Dn input to the LE input
7
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
8
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
9
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
10
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
NOTES
11
1997 Mar 12
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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