74LVC245ABX [NXP]
Octal bus transceiver; 3-state; 八路总线收发器;三态
| 型号： | 74LVC245ABX |
| 厂家： | 
NXP |
| 描述： | Octal bus transceiver; 3-state |
| 文件： | 总17页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Rev. 05 — 25 August 2009
Product data sheet
1. General description
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features an output
enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features
I 5 V tolerant inputs/outputs for interfacing with 5 V logic
I Wide supply voltage range from 1.2 V to 3.6 V
I CMOS low-power consumption
I Direct interface with TTL levels
I Inputs accept voltages up to 5.5 V
I High-impedance when VCC = 0 V
I Bushold on all data inputs (74LVCH245A only)
I Complies with JEDEC standard no. 8-1A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC245AD
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVCH245AD
74LVC245ADB
74LVCH245ADB
74LVC245APW
74LVCH245APW
74LVC245ABQ
74LVCH245ABQ
SSOP20
TSSOP20
DHVQFN20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
SOT764-1
74LVC245ABX
−40 °C to +125 °C
DHXQFN20U
plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
SOT1045-1
74LVCH245ABX
4. Functional diagram
DIR
1
OE
19
A0
2
B0
18
A1
3
B1
17
A2
4
19
G3
1
B2
16
3EN1
3EN2
A3
5
B3
15
1
A4
6
18
2
2
B4
14
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A5
7
B5
13
A6
8
B6
12
A7
9
B7
11
mna175
mna174
Fig 1. Logic diagram
Fig 2. IEC logic symbol
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
2 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVC245A
74LVCH245A
terminal 1
index area
74LVC245A
74LVCH245A
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
A0
A1
A2
A3
A4
A5
A6
A7
OE
B0
B1
B2
B3
B4
B5
B6
1
2
20
19
18
17
16
15
14
13
12
11
DIR
A0
V
CC
OE
B0
B1
B2
B3
B4
B5
B6
B7
3
A1
4
A2
5
A3
6
A4
(1)
GND
7
A5
8
A6
9
A7
001aak293
10
GND
Transparent top view
001aak292
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3. Pin configuration for SO20 and (T)SSOP20
Fig 4. Pin configuration for DHVQFN20 and
DHXQFN20U
5.2 Pin description
Table 2.
Symbol
DIR
Pin description
Pin
Description
1
direction control
A0 to A7
GND
2, 3, 4, 5, 6, 7, 8, 9
data input/output
ground (0 V)
10
B0 to B7
OE
18, 17, 16, 15, 14, 13, 12, 11
data input/output
output enable input (active LOW)
supply voltage
19
20
VCC
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
3 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
6. Functional description
Table 3.
Function selection[1]
Inputs
Inputs/outputs
OE
L
DIR
An
Bn
L
An = Bn
inputs
Z
inputs
Bn = An
Z
L
H
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW
output 3-state
mA
V
[2]
[2]
VO
−0.5
−0.5
-
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20U packages: above 60 °C derate linearly with 4.5 mW/K.
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
4 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
maximum speed
performance
2.7
-
3.6
V
functional
1.2
0
-
-
-
-
-
-
-
3.6
5.5
VCC
5.5
+125
20
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
−40
0
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C Unit
Min
VCC
2.0
-
Max
VIH
HIGH-level input VCC = 1.2 V
voltage
VCC
-
-
-
-
-
-
-
-
V
V
V
V
VCC = 2.7 V to 3.6 V
2.0
VIL
LOW-level input
voltage
VCC = 1.2 V
VCC = 2.7 V to 3.6 V
-
-
0
0
0.8
-
0.8
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = −100 µA;
VCC − 0.2 VCC
-
VCC − 0.3
-
V
V
CC = 2.7 V to 3.6 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
2.2
2.4
2.2
-
-
-
-
-
-
2.05
2.25
2.0
-
-
-
V
V
V
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 µA;
CC = 2.7 V to 3.6 V
-
0
0.20
-
0.3
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
0.40
0.55
±5
-
-
-
0.6
0.8
V
V
[2]
II
input leakage
current
VI = 5.5 V or GND; VCC = 3.6 V
±0.1
±20 µA
[2][3]
IOZ
OFF-state output VI = VIH or VIL;
current VO = 5.5 V or GND;
CC = 3.6 V
-
±0.1
±5
-
±20 µA
V
IOFF
ICC
power-off leakage VI or VO = 5.5 V; VCC = 0.0 V
current
-
-
-
±0.1
0.1
5
±10
10
-
-
-
±20 µA
supply current
VI = VCC or GND; IO = 0 A;
CC = 3.6 V
40
µA
V
∆ICC
additional supply per input pin; VI = VCC − 0.6 V;
current IO = 0 A; VCC = 2.7 V to 3.6 V
500
5000 µA
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
5 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C Unit
Min
Max
CI
input capacitance
-
4.0
10
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
-
[4][5]
[4][5]
[4][6]
[4][6]
IBHL
bus hold LOW
current
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V
75
-
-
-
-
-
-
-
-
60
−60
500
−500
-
-
-
-
µA
µA
µA
µA
IBHH
bus hold HIGH
current
−75
500
−500
IBHLO
IBHHO
bus hold LOW
overdrive current
bus hold HIGH
VCC = 3.6 V
overdrive current
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter IOZ includes the input leakage current.
[4] Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified VI level.
[6] The specified overdrive current at the data input forces the data input to the opposite input state.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[2] Max
−40 °C to +125 °C Unit
Min
Max
[1]
tpd
propagation
delay
An to Bn; see Figure 5
VCC = 1.2 V
-
17.0
3.4
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
7.3
6.3
1.5
1.5
9.5
8.0
[3]
[1]
VCC = 3.0 V to 3.6 V
OE to An or Bn; see Figure 6
VCC = 1.2 V
2.9
ten
enable time
disable time
-
22.0
5.0
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
9.5
8.5
1.5
1.5
12.0
11.0
[3]
[1]
VCC = 3.0 V to 3.6 V
OE to An or Bn; see Figure 6
VCC = 1.2 V
4.0
tdis
-
12.0
3.6
3.4
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
1.5
1.7
-
8.0
7.0
1.0
1.5
1.7
-
10.0
9.0
1.5
[3]
[4]
VCC = 3.0 V to 3.6 V
tsk(o)
output skew
time
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
6 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[2] Max
15
−40 °C to +125 °C Unit
Min
Max
[5]
CPD
power
per buffer; VI = GND to VCC; VCC = 3.3 V
-
-
-
-
pF
dissipation
capacitance
[1] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[2] Typical values are measured at Tamb = 25 °C.
[3] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V.
[4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. AC waveforms
V
I
An, Bn input
GND
V
M
V
M
t
t
PLH
PHL
V
OH
V
V
M
Bn, An output
M
V
OL
mna176
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
7 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
V
I
OE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna367
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 8. Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
0.5 × VCC
1.5 V
1.5 V
0.5 × VCC
1.5 V
VOL + 0.1 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
OH − 0.1 V
2.7 V
2.7 V
2.7 V
OH − 0.3 V
OH − 0.3 V
3.0 V to 3.6 V
1.5 V
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
8 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
1.2 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
50 pF
50 pF
500 Ω[1]
500 Ω
500 Ω
2.7 V
2.7 V
2.7 V
open
GND
3.0 V to 3.6 V
open
GND
[1] The circuit performs better when RL = 1 kΩ.
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
9 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 8. Package outline SOT163-1 (SO20)
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
10 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 9. Package outline SOT339-1 (SSOP20)
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
11 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 10. Package outline SOT360-1 (TSSOP20)
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
12 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 11. Package outline SOT764-1 (DHVQFN20)
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
13 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package;
no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
SOT1045-1
D
B
A
E
A
A
1
detail X
terminal 1
index area
terminal 1
index area
e
1
C
M
M
v
C
C
A
B
b
e
L
1
y
y
w
C
1
2
9
L
10
11
1
E
e
h
20
19
12
X
D
h
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
D
h
E
E
e
e
1
L
L
v
w
y
y
1
h
1
max
0.05 0.30
0.00 0.18
4.6
4.4
3.35
3.05
2.6
2.4
1.35
1.05
0.45 0.13
0.25 0.05
mm
0.5
0.5
3.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-01
09-08-04
SOT1045-1
- - -
Fig 12. Package outline SOT1045-1 (DHXQFN20U)
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
14 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20090825 Product data sheet
Change notice
Supersedes
74LVC_LVCH245A_5
Modifications:
-
74LVC_LVCH245A_4
• New SOT1045-1 package outline drawing (DHXQFN20U package).
20090703 Product data sheet 74LVC_LVCH245A_3
74LVC_LVCH245A_4
Modifications:
-
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74LVC245ABX and 74LVCH245ABX (DHXQFN20U package)
74LVC_LVCH245A_3
20030507
Product specification
Product specification
Product specification
-
-
-
74LVC245A_74LVCH245A_2
74LVC245A_74LVCH245A_2 20020620
74LVC245A_74LVCH245A_1 19971219
74LVC245A_74LVCH245A_1
-
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
15 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH245A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 25 August 2009
16 of 17
74LVC245A; 74LVCH245A
NXP Semiconductors
Octal bus transceiver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 August 2009
Document identifier: 74LVC_LVCH245A_5
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