74LVC245APW-Q100_技术文档

74LVC245A-Q100; 74LVCH245A-Q100

Octal bus transceiver; 3-state

Rev. 1 — 3 September 2012

Product data sheet

1. General description

The 74LVC245A-Q100; 74LVCH245A-Q100 are 8-bit transceivers featuring non-inverting

3-state bus compatible outputs in both send and receive directions. The device features

an output enable (OE) input for easy cascading and a send/receive (DIR) input for

direction control. OE controls the outputs so that the buses are effectively isolated.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

The 74LVCH245A-Q100 bus hold on data inputs eliminates the need for external pull-up

resistors to hold unused inputs.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Inputs accept voltages up to 5.5 V

 High-impedance when V_CC= 0 V

 Bus hold on all data inputs (74LVCH245A-Q100 only)

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC245AD-Q100

74LVCH245AD-Q100

40 C to +125 C

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74LVC245APW-Q100 40 C to +125 C

TSSOP20

plastic thin shrink small outline package;

20 leads; body width 4.4 mm

SOT360-1

74LVCH245APW-Q100

74LVC245ABQ-Q100

74LVCH245ABQ-Q100

40 C to +125 C

DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1

very thin quad flat package; no leads;

20 terminals; body 2.5  4.5  0.85 mm

4. Functional diagram

DIR

1

OE

19

A0

2

B0

B1

18

17

A1

3

A2

4

19

1

G3

B2

B3

B4

B5

B6

B7

16

15

3EN1

3EN2

A3

5

1

A4

6

18

2

14

13

12

11

3

4

5

6

7

8

9

17

16

15

14

13

12

11

A5

7

A6

8

A7

9

mna174

mna175

Fig 1. Logic diagram

Fig 2. IEC logic symbol

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

2 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

5. Pinning information

5.1 Pinning

74LVC245A-Q100

74LVCH245A-Q100

terminal 1

index area

74LVC245A-Q100

74LVCH245A-Q100

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

A0

A1

A2

A3

A4

A5

A6

A7

OE

B0

B1

B2

B3

B4

B5

B6

1

2

20

19

18

17

16

15

14

13

12

11

DIR

A0

V

CC

OE

B0

B1

B2

B3

B4

B5

B6

B7

3

A1

4

A2

5

A3

6

A4

(1)

GND

7

A5

8

A6

9

A7

aaa-003143

Transparent top view

10

GND

aaa-003142

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 3. Pin configuration for SO20 and TSSOP20

Fig 4. Pin configuration for DHVQFN20

5.2 Pin description

Table 2.

Symbol

DIR

Pin description

Description

1

direction control

A0 to A7

GND

2, 3, 4, 5, 6, 7, 8, 9

data input/output

ground (0 V)

10

B0 to B7

OE

18, 17, 16, 15, 14, 13, 12, 11

data input/output

output enable input (active LOW)

supply voltage

19

20

V_CC

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

3 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

6. Functional description

Table 3.

Function selection^[1]

Inputs

Inputs/outputs

OE

L

DIR

An

Bn

L

An = Bn

inputs

Z

inputs

Bn = An

Z

L

H

X

H

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

50

V_CC+ 0.5

+6.5

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output HIGH or LOW

output 3-state

mA

V

[2]

V_O

0.5

-

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO20 package: above 70 C derate linearly with 8 mW/K.

For TSSOP20 package: above 60 C derate linearly with 5.5 mW/K.

For DHVQFN20 package: above 60 C derate linearly with 4.5 mW/K.

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

4 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

Unit

V

supply voltage

-

functional

3.6

5.5

V

V_I

input voltage

V

V_O

output voltage

output HIGH or LOW

output 3-state

0

V_CC

5.5

+125

20

V

0

V

T_amb

ambient temperature

in free air

40

0

C

ns/V

t/V

input transition rise and fall rate

V_CC= 1.2 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Min Max

1.08

Unit

Min

Typ^[1]

Max

V_IH

HIGH-level

V_CC= 1.2 V

1.08

-

V

input voltage

V_CC= 1.65 V to 1.95 V

0.65  V_CC

-

0.65  V_CC

V

_CC= 2.3 V to 2.7 V

1.7

-

1.7

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

2.0

V_IL

LOW-level

-

0.12

-

0.12

input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

voltage

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

-

0.55

5

0.8

V

[2]

I_I

input leakage V_I= 5.5 V or GND;

current V_CC= 3.6 V

0.1

20

A

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

5 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

[3]

I_OZ

OFF-state

V_I= V_IHor V_IL;

-

0.1

5

-

20

A

output current V_O= 5.5 V or GND;

_CC= 3.6 V

V

I_OFF

power-off

leakage

current

V_Ior V_O= 5.5 V; V_CC= 0.0

V

-

0.1

10

-

20

A

I_CC

supply

current

V_I= V_CCor GND; I_O= 0 A;

-

0.1

5

10

-

40

A

V_CC= 3.6 V

I_CC

additional

supply

current

per input pin;

V_I= V_CC 0.6 V; I_O= 0 A;

V_CC= 2.7 V to 3.6 V

500

5000

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

-

4.0

10

-

pF

C_I/O

I_BHL

input/output

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

[4][5]

bus hold

LOW current

V_CC= 1.65; V_I= 0.58 V

V_CC= 2.3; V_I= 0.7 V

V_CC= 3.0; V_I= 0.8 V

V_CC= 1.65; V_I= 1.07 V

V_CC= 2.3; V_I= 1.7 V

V_CC= 3.0; V_I= 2.0 V

V_CC= 1.95 V

10

30

-

10

25

-

A

75

60

I_BHH

bus hold

HIGH current

10

30

75

200

300

500

10

25

60

200

300

500

I_BHLO

bus hold

LOW

overdrive

current

V_CC= 2.7 V

[4][6]

V_CC= 3.6 V

I_BHHO

bus hold

HIGH

overdrive

current

V_CC= 1.95 V

V_CC= 2.7 V

V_CC= 3.6 V

200

300

500

-

200

300

500

-

A

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

[2] The bus hold circuit is switched off when V_I> V_CCallowing 5.5 V on the input terminal.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

[4] Valid for data inputs of bus hold parts only (74LVCH245A-Q100). Note that control inputs do not have a bus hold circuit.

[5] The specified sustaining current at the data input holds the input below the specified V_Ilevel.

[6] The specified overdrive current at the data input forces the data input to the opposite input state.

74LVC_LVCH245A_Q100

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Product data sheet

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6 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[2]

Max

Min

Max

[1]

t_pd

t_en

t_dis

propagation

delay

nAn to nBn; nBn to nAn; see Figure 5

V_CC= 1.2 V

-

17.0

6.5

3.4

2.9

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

1.5

14.6

7.6

7.3

6.3

1.5

1.0

1.5

16.9

8.7

9.5

8.0

V_CC= 3.0 V to 3.6 V

nOE to nAn, nBn; see Figure 6

V_CC= 1.2 V

enable time

-

22.0

8.3

4.6

4.8

3.7

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.9

1.5

19.5

10.7

9.5

1.9

1.5

22.5

12.4

12.0

11.0

V_CC= 3.0 V to 3.6 V

nOE to nAn, nBn; see Figure 6

V_CC= 1.2 V

8.5

disable time

-

12.0

5.5

3.1

3.9

3.6

-

ns

V_CC= 1.65 V to 1.95 V

2.9

1.0

1.5

1.7

-

12.3

7.1

8.0

7.0

1.0

2.9

1.0

1.5

1.7

-

14.2

8.2

V

_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

10.0

9.0

V_CC= 3.0 V to 3.6 V

[3]

[4]

t_sk(o)

C_PD

output skew

time

1.5

power

dissipation

capacitance

per input; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

-

7.7

11.3

14.4

-

pF

V_CC= 3.0 V to 3.6 V

[1] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[2] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs.

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

7 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

11. AC waveforms

V

I

An, Bn input

GND

V

M

t

PLH

PHL

V

OH

V

M

Bn, An output

M

V

OL

mna176

See Table 8 for measurement points

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times

V

I

OE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna367

See Table 8 for measurement points

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 6. Enable and disable times

Table 8. Measurement points

Supply voltage

V_CC

V_M

Input

V_I

t_r= t_f

V_X

V_Y

1.2 V

0.5  V_CC

1.5 V

V_CC

2.7 V

 2.5 ns

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH 0.15 V

V_OH 0.3 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

8 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 7. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

9 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

12. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 8. Package outline SOT163-1 (SO20)

74LVC_LVCH245A_Q100

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Product data sheet

Rev. 1 — 3 September 2012

10 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 9. Package outline SOT360-1 (TSSOP20)

74LVC_LVCH245A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 September 2012

11 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

9

L

1

10

E

h

e

20

11

19

12

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

4.6

4.4

3.15

2.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT764-1

- - -

MO-241

- - -

Fig 10. Package outline SOT764-1 (DHVQFN20)

74LVC_LVCH245A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 September 2012

12 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

Military

MIL

14. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

Change notice

Supersedes

74LVC_LVCH245A_Q100 v.1 20120903

Product data sheet

-

74LVC_LVCH245A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 September 2012

13 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74LVC_LVCH245A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 September 2012

14 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC_LVCH245A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 September 2012

15 of 16

74LVC_LVCH245A_Q100

NXP Semiconductors

Octal bus transceiver; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 15

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 September 2012

Document identifier: 74LVC_LVCH245A_Q100


型号：	74LVC245APW-Q100
厂家：	NXP
描述：	Octal bus transceiver; 3-state 八路总线收发器;三态总线收发器逻辑集成电路光电二极管
文件：	总16页 (文件大小：243K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC245APW-Q100 [NXP]

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