74LVC257ADB,112_技术文档

74LVC257A

Quad 2-input multiplexer with 5 V tolerant inputs/outputs;

3-state

Rev. 6 — 28 November 2011

Product data sheet

1. General description

The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of

data from two sources and are controlled by a common data select input (pin S). The data

inputs from source 0 (pins 1I0 to 4I0) are selected when pin S is LOW and the data inputs

from source 1 (pins 1I1 to 4I1) are selected when pin S is HIGH. Data appears at the

outputs (pins 1Y to 4Y) in true (non-inverting) form from the selected inputs. The device is

the logic implementation of a 4-pole, 2-position switch, where the position of the switch is

determined by the logic levels applied to pin S. The outputs are forced to a

high-impedance OFF-state when pin OE is HIGH.

Inputs can be driven from either 3.3 V or 5.0 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

2. Features and benefits

 5 V tolerant inputs/outputs, for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Output drive capability 50  transmission lines at 85 C

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC257AD

40 C to +125 C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74LVC257ADB 40 C to +125 C

74LVC257APW 40 C to +125 C

74LVC257ABQ 40 C to +125 C

SSOP16

TSSOP16

plastic shrink small outline package; 16 leads;

body width 5.3 mm

SOT338-1

SOT403-1

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1

thin quad flat package; no leads; 16 terminals;

body 2.5  3.5  0.85 mm

4. Functional diagram

1

G1

15

1I0

1I1

2I0

2I1

2

3

EN

2

MUX

1

1Y

2Y

3Y

4Y

4

7

5

4

7

3

5

6

11

10

14

13

9

3I0

3I1

4I0

4I1

12

11

10

14

13

9

12

S

1

OE

mna865

15

mna866

Fig 1. Logic diagram

Fig 2. IEC logic symbol

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

2 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

1I1

1Y

1I0

2I1

2Y

2I0

1I0

2

1Y

2Y

3Y

4Y

4

7

1I1

3

3I1

2I0

5

3Y

3-STATE

MULTI-

PLEXER

OUTPUTS

2I1

6

3I0

SELECTOR

3I0

3I1

4I0

4I1

11

10

14

13

9

4I1

4Y

12

4I0

OE

S

1

15 OE

S

mna867

mna868

Fig 3. Functional diagram

Fig 4. Logic diagram

5. Pinning information

5.1 Pinning

74LVC257A

terminal 1

index area

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

S

1I0

V

CC

OE

4I0

4I1

4Y

2

3

4

5

6

7

15

14

13

12

11

10

1I0

1I1

1Y

2I0

2I1

2Y

OE

4I0

4I1

4Y

1I1

1Y

257A

2I0

3I0

3I1

(1)

GND

2I1

3I0

3I1

3Y

2Y

001aad098

GND

Transparent top view

001aad097

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration for SO24 and (T)SSOP24

Fig 6. Pin configuration for DHVQFN24

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

3 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

5.2 Pin description

Table 2.

Symbol

S

Pin description

1

Description

common data select input

data input from source 0

data input from source 1

3-state multiplexer output

data input from source 0

data input from source 1

3-state multiplexer output

ground (0 V)

1I0

2

1I1

3

1Y

4

2I0

5

2I1

6

2Y

7

GND

3Y

8

9

3-state multiplexer output

data input from source 1

data input from source 0

3-state multiplexer output

data input from source 1

data input from source 0

3I1

10

11

12

13

14

15

16

3I0

4Y

4I1

4I0

OE

3-state output enable input (active LOW)

supply voltage

V_CC

6. Functional description

Table 3.

Function table^[1]

Input

Output

OE

H

L

S

X

H

L

nI0

X

nI1

X

nY

Z

X

L

X

H

X

H

L

H

X

H

[1] H = HIGH voltage level

L = LOW voltage level

X = don’t care

Z = high-impedance OFF-state

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

4 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0

mA

V

[1]

V_I

+6.5

50

V_CC+ 0.5

+6.5

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0

HIGH or LOW state

output 3-state

mA

V

[2]

V_O

0.5

-

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO16 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

For DHVQFN16 packages: above 60 C the value of P_totderates linearly with 4.5 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

5.5

+125

20

V

V_O

output voltage

HIGH or LOW state

3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

0

C

ns/V

t/V

input transition rise and fall

rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0

10

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

5 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

0.65  V_CC

-

0.65  V_CC

-

1.7

-

1.7

-

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level

input voltage

-

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

-

0.2

-

0.3

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

0.55

5

0.8

V

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

0.1

20

A

I_OZ

OFF-state

output

current

V_I= V_IHor V_IL; V_CC= 3.6 V;

V_O= 5.5 V or GND;

-

0.1

5

-

20

A

I_OFF

power-off

leakage

current

V_CC= 0 V; V_Ior V_O= 5.5 V

10

I_CC

supply

current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

5

10

-

40

A

I_CC

additional

supply

current

per input pin;

V_CC= 2.7 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

500

5000

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

6 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

[3]

t_pd

propagation delay

nI0, nI1 to nY; see Figure 7

V_CC= 1.2 V

-

16

5.2

2.8

2.4

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

10.6

5.5

5.4

4.6

1.5

1.0

12.3

6.4

7.0

6.0

V_CC= 3.0 V to 3.6 V

S to nY; see Figure 7

V_CC= 1.2 V

-

18

6.0

3.2

2.7

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

14.8

7.7

7.5

6.4

1.0

17.1

8.9

9.5

8.0

V_CC= 3.0 V to 3.6 V

OE to nY; see Figure 8

V_CC= 1.2 V

t_en

enable time

-

15

5.8

3.3

3.4

2.7

-

ns

V_CC= 1.65 V to 1.95 V

1.5

1.0

12.7

7.0

6.7

5.6

1.5

1.0

14.7

8.1

8.5

7.0

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

OE to nY; see Figure 8

V_CC= 1.2 V

t_dis

disable time

-

8

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.2

0.5

1.5

1.0

-

4.0

2.2

3.0

2.8

-

8.2

4.4

4.7

4.3

1.0

2.2

0.5

1.5

1.0

-

9.4

5.1

6.0

5.5

1.5

V_CC= 3.0 V to 3.6 V

t_sk(o)

output skew time

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

7 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[4]

C_PD

power dissipation

capacitance

per input; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

-

8.0

11.4

14.4

-

pF

V_CC= 3.0 V to 3.6 V

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

11. Waveforms

V

CC

V

S, nl0, nl1 input

GND

M

t

PLH

PHL

V

OH

V

nY output

M

mna869

V

OL

V_M= 1.5 V at V_CC 2.7 V;

V_M= 0.5  V_CCat V_CC< 2.7 V;

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 7. Input (S, nI0 and nI1) to output (nY) propagation delays

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

8 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

V

I

OE input

output

V

M

t

GND

t

PLZ

PZL

V

CC

V

LOW-to-OFF

OFF-to-LOW

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

V

HIGH-to-OFF

OFF-to-HIGH

M

GND

output

enabled

output

enabled

output

disabled

mna870

V_M= 1.5 V at V_CC 2.7 V.

V_M= 0.5  V_CCat V_CC< 2.7 V.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

V_X= V_OL+ 0.3 V at V_CC 2.7 V;

V_X= V_OL+ 0.15 V at V_CC 2.7 V;

V

_Y= V_OH 0.3 V at V_CC 2.7 V;

V_Y= V_OH 0.15 V at V_CC 2.7 V.

Fig 8. 3-state enable and disable times

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

9 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 8.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 9. Test circuit for measuring switching times

Table 8.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

10 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 10. Package outline SOT109-1 (SO16)

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

11 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig 11. Package outline SOT338-1 (SSOP16)

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

12 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 12. Package outline SOT403-1 (TSSOP16)

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

13 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig 13. Package outline SOT763-1 (DHVQFN16)

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

14 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

13. Abbreviations

Table 9.

Acronym

CDM

DUT

Abbreviations

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 10. Revision history

Document ID

74LVC257A v.6

Modifications:

Release date

20111128

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVC257A v.5

• Value changes for t_pd, t_enand t_disin Table 7 “Dynamic characteristics”

• Typographical errors corrected

74LVC257A v.5

Modifications:

20111108

Product data sheet

-

74LVC257A v.4

• The format of this document has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVC257A v.4

74LVC257A v.3

74LVC257A v.2

74LVC257A v.1

040123

031117

980729

-

Product specification

-

74LVC257A v.3

74LVC257A v.2

74LVC257A v.1

-

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

15 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

16 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC257A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 28 November 2011

17 of 18

74LVC257A

NXP Semiconductors

Quad 2-input multiplexer with 5V tolerant; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 November 2011

Document identifier: 74LVC257A


型号：	74LVC257ADB,112
厂家：	NXP
描述：	74LVC257A - Quad 2-input multiplexer with 5 V tolerant inputs/outputs; 3-state SSOP1 16-Pin 光电二极管逻辑集成电路
文件：	总18页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC257ADB,112 [NXP]

相关型号：

74LVC257ADB,118

74LVC257ADB-T

74LVC257APW

74LVC257APW

74LVC257APW,112

74LVC257APW-T

74LVC257APWDH

74LVC258D-T

74LVC258PW-T

74LVC259D-T

74LVC259DB-T

74LVC2623AD