74LVC2G06GW [NXP]

Inverters with open-drain outputs; 逆变器具有漏极开路输出
74LVC2G06GW
型号: 74LVC2G06GW
厂家: NXP    NXP
描述:

Inverters with open-drain outputs
逆变器具有漏极开路输出

栅极 逻辑集成电路 光电二极管
文件: 总14页 (文件大小:84K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
74LVC2G06  
Inverters with open-drain outputs  
Product specification  
2004 Sep 10  
Supersedes data of 2003 Aug 25  
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
FEATURES  
DESCRIPTION  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
The 74LVC2G06 is a high-performance, low-power,  
low-voltage, Si-gate CMOS device and superior to most  
advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. This  
feature allows the use of this device in a mixed  
3.3 V and 5 V environment.  
Complies with JEDEC standard:  
– JESD8-7 (1.65 V to 1.95 V)  
– JESD8-5 (2.3 V to 2.7 V)  
Schmitt trigger action at all inputs makes the circuit tolerant  
for slower input rise and fall time.  
– JESD8B/JESD36 (2.7 V to 3.6 V).  
• −24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
This device is fully specified for partial power-down  
applications using Ioff. The Ioff circuitry disables the output,  
preventing the damaging backflow current through the  
device when it is powered down.  
The 74LVC2G06 provides two inverting buffers.  
The output of this device is an open drain and can be  
connected to other open-drain outputs to implement  
active-LOW wired-OR or active-HIGH wired-AND  
functions.  
ESD protection:  
– HBM EIA/JESD22-A114-B exceeds 2000 V  
– MM EIA/JESD22-A115-A exceeds 200 V.  
Specified from 40 °C to +85 °C and  
40 °C to +125 °C.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C.  
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
ns  
tPLZ/tPZL  
propagation delay input nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ  
3.2  
VCC = 2.5 V; CL = 30 pF; RL = 500 2.0  
VCC = 2.7 V; CL = 50 pF; RL = 500 2.6  
ns  
ns  
ns  
ns  
pF  
pF  
VCC = 3.3 V; CL = 50 pF; RL = 500 2.3  
VCC = 5.0 V; CL = 50 pF; RL = 500 1.6  
CI  
input capacitance  
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2  
2.5  
CPD  
5.9  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = total load switching outputs;  
(CL × VCC2 × fo) = sum of the outputs.  
2. The condition is VI = GND to VCC  
.
2004 Sep 10  
2
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
FUNCTION TABLE  
See note 1.  
INPUT  
nA  
OUTPUT  
nY  
L
Z
L
H
Note  
1. H = HIGH voltage level;  
L = LOW voltage level;  
Z = high-impedance OFF-state.  
ORDERING INFORMATION  
PACKAGE  
PACKAGE MATERIAL  
TYPE NUMBER  
TEMPERATURE RANGE  
PINS  
CODE  
MARKING  
74LVC2G06GW  
74LVC2G06GV  
74LVC2G06GM  
40 °C to +125 °C  
40 °C to +125 °C  
40 °C to +125 °C  
6
6
6
SC-88  
SC-74  
XSON6  
plastic  
plastic  
plastic  
SOT363  
SOT457  
SOT886  
V6  
V06  
V6  
PINNING  
PIN  
1
SYMBOL  
DESCRIPTION  
1A  
data input  
2
GND  
2A  
ground (0 V)  
data input  
3
4
2Y  
data output  
supply voltage  
data output  
5
VCC  
1Y  
6
06  
1A  
GND  
2A  
1
2
3
6
5
4
1Y  
1
2
3
6
5
4
1A  
1Y  
V
V
CC  
GND  
2A  
06  
CC  
2Y  
2Y  
001aab669  
001aab668  
Transparent top view  
Fig.1 Pin configuration SC-88 and SC-74.  
Fig.2 Pin configuration XSON6.  
2004 Sep 10  
3
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
handbook, halfpage  
handbook, halfpage  
1A  
2A  
1Y  
6
4
1
3
1
3
6
1A  
2A  
1Y  
2Y  
4
2Y  
MNB096  
MNB095  
Fig.3 Logic symbol.  
Fig.4 IEEE/IEC logic symbol.  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
VCC  
PARAMETER  
supply voltage  
CONDITIONS  
MIN.  
1.65  
MAX.  
5.5  
UNIT  
V
VI  
input voltage  
0
5.5  
VCC  
5.5  
+125  
20  
V
VO  
output voltage  
active mode  
0
V
VCC = 0 V; Power-down mode  
0
V
Tamb  
tr, tf  
operating ambient temperature  
input rise and fall times  
40  
0
°C  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
ns/V  
ns/V  
0
10  
2004 Sep 10  
4
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).  
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT  
VCC supply voltage 0.5 +6.5  
V
IIK  
input diode current  
input voltage  
VI < 0 V  
note 1  
50  
+6.5  
50  
6.5  
mA  
V
VI  
0.5  
IOK  
VO  
output diode current  
output voltage  
VO < 0 V  
mA  
V
active mode; notes 1 and 2  
0.5  
Power-down mode; notes 1 and 2 0.5  
+6.5  
50  
V
IO  
output source or sink current  
VCC or GND current  
storage temperature  
power dissipation  
VO = 0 V to 6.5 V  
mA  
mA  
°C  
mW  
ICC, IGND  
Tstg  
±100  
+150  
300  
65  
Ptot  
Tamb = 40 °C to +125 °C  
Notes  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
2004 Sep 10  
5
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
DC CHARACTERISTICS  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
TEST CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
OTHER  
VCC (V)  
Tamb = 40 °C to +85 °C; note 1  
VIH  
HIGH-level input voltage  
LOW-level input voltage  
1.65 to 1.95 0.65 × VCC  
V
V
V
V
V
V
V
V
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.65 to 1.95  
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.7  
2.0  
0.7 × VCC  
VIL  
0.35 × VCC  
0.7  
0.8  
0.3 × VCC  
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 100 µA  
IO = 4 mA  
IO = 8 mA  
IO = 12 mA  
IO = 24 mA  
IO = 32 mA  
1.65 to 5.5  
1.65  
0.1  
V
0.45  
0.3  
V
2.3  
V
2.7  
0.4  
V
3.0  
0.55  
0.55  
±5  
V
4.5  
V
ILI  
input leakage current  
VI = 5.5 V or GND  
1.65 to 5.5  
5.5  
±0.1  
±0.1  
µA  
µA  
IOZ  
3-state output OFF-state VI = VIH or VIL;  
±10  
current  
VO = VCC or GND  
VI or VO = 5.5 V  
Ioff  
power OFF leakage  
current  
0
±0.1  
0.1  
5
±10  
10  
µA  
µA  
µA  
ICC  
ICC  
quiescent supply current VI = VCC or GND;  
IO = 0 A  
5.5  
additional quiescent  
supply current per pin  
VI = VCC 0.6 V;  
IO = 0 A  
2.3 to 5.5  
500  
2004 Sep 10  
6
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
TEST CONDITIONS  
OTHER VCC (V)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
Tamb = 40 °C to +125 °C  
VIH  
HIGH-level input voltage  
LOW-level input voltage  
1.65 to 1.95 0.65 × VCC  
V
V
V
V
V
V
V
V
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.65 to 1.95  
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.7  
2.0  
0.7 × VCC  
VIL  
0.35 × VCC  
0.7  
0.8  
0.3 × VCC  
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 100 µA  
IO = 4 mA  
IO = 8 mA  
IO = 12 mA  
IO = 24 mA  
IO = 32 mA  
1.65 to 5.5  
1.65  
0.1  
V
0.70  
0.45  
0.60  
0.80  
0.80  
±20  
±10  
V
2.3  
V
2.7  
V
3.0  
V
4.5  
V
ILI  
input leakage current  
VI = 5.5 V or GND  
1.65 to 5.5  
5.5  
µA  
µA  
IOZ  
3-state output OFF-state VI = VIH or VIL;  
current  
VO = VCC or GND  
VI or VO = 5.5 V  
Ioff  
power OFF leakage  
current  
0
±20  
40  
µA  
µA  
µA  
ICC  
ICC  
quiescent supply current VI = VCC or GND;  
IO = 0 A  
5.5  
additional quiescent  
supply current per pin  
VI = VCC 0.6 V;  
IO = 0 A  
2.3 to 5.5  
5000  
Note  
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  
2004 Sep 10  
7
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
AC CHARACTERISTICS  
GND = 0 V.  
TEST CONDITIONS  
WAVEFORMS CC (V)  
SYMBOL  
PARAMETER  
MIN.  
TYP. MAX. UNIT  
V
Tamb = 40 °C to +85 °C; note 1  
tPLZ/tPZL propagation delay input nA to  
output nY  
see Figs 5 and 6  
1.65 to 1.95 1.0  
3.2  
2.0  
2.6  
2.3  
1.6  
6.5  
3.9  
4.2  
3.4  
2.9  
ns  
ns  
ns  
ns  
ns  
2.3 to 2.7  
2.7  
0.5  
1.0  
0.5  
0.5  
3.0 to 3.6  
4.5 to 5.5  
Tamb = 40 °C to +125 °C  
tPLZ/tPZL  
propagation delay input nA to  
output nY  
see Figs 5 and 6  
1.65 to 1.95 1.0  
8.2  
4.9  
5.3  
4.3  
3.7  
ns  
ns  
ns  
ns  
ns  
2.3 to 2.7  
2.7  
0.5  
1.0  
0.5  
0.5  
3.0 to 3.6  
4.5 to 5.5  
Note  
1. All typical values are measured at Tamb = 25 °C and at VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.  
AC WAVEFORMS  
V
I
V
nA input  
M
GND  
t
t
PZL  
PLZ  
V
CC  
nY output  
V
M
V
V
X
OL  
MNA529  
INPUT  
VCC  
VM  
VX  
VI  
tr = tf  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5 × VCC  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOL + 0.3 V  
VCC  
VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
0.5 × VCC  
1.5 V  
2.7 V  
2.7 V  
VCC  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
0.5 × VCC  
VOL and VOH are typical output voltage drop that occur with the output load.  
Fig.5 The input (nA) to output (nY) propagation delays.  
8
2004 Sep 10  
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
V
EXT  
V
CC  
R
L
V
I
V
O
PULSE  
GENERATOR  
D.U.T.  
C
L
R
L
R
T
mna616  
VEXT  
VCC  
VI  
VCC  
CL  
RL  
1 kΩ  
tPZL/tPLZ  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
2 × VCC  
2 × VCC  
6 V  
VCC  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
2.7 V  
2.7 V  
VCC  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
6 V  
2 × VCC  
Definitions for test circuit:  
RL = Load resistor.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
Fig.6 Load circuitry for switching times.  
2004 Sep 10  
9
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
PACKAGE OUTLINES  
Plastic surface mounted package; 6 leads  
SOT363  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B  
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
UNIT  
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max  
0.30  
0.20  
1.1  
0.8  
0.25  
0.10  
2.2  
1.8  
1.35  
1.15  
2.2  
2.0  
0.45  
0.15  
0.25  
0.15  
mm  
0.1  
1.3  
0.65  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
97-02-28  
SOT363  
SC-88  
2004 Sep 10  
10  
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
Plastic surface mounted package; 6 leads  
SOT457  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
c
1
2
3
L
p
e
b
p
w
M B  
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
b
c
D
E
e
H
L
Q
v
w
y
p
p
E
0.1  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
97-02-28  
01-05-04  
SOT457  
SC-74  
2004 Sep 10  
11  
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm  
SOT886  
b
1
2
3
4×  
(2)  
L
L
1
e
6
5
4
e
1
e
1
6×  
(2)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.25  
0.17  
1.5  
1.4  
1.05  
0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.6  
0.5  
Notes  
1. Including plating thickness.  
2. Can be visible in some manufacturing processes.  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
04-07-15  
04-07-22  
SOT886  
MO-252  
2004 Sep 10  
12  
Philips Semiconductors  
Product specification  
Inverters with open-drain outputs  
74LVC2G06  
DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2004 Sep 10  
13  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2004  
SCA76  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
R20/02/pp14  
Date of release: 2004 Sep 10  
Document order number: 9397 750 13774  

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DIODES

74LVC2G07

Buffers with open-drain outputs
NXP

74LVC2G07

DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
DIODES

74LVC2G07-Q100

Buffers with open-drain outputs
NEXPERIA

74LVC2G07DW

DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
DIODES

74LVC2G07DW-7

DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
DIODES

74LVC2G07FW4

DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
DIODES