74LVC2G125GM [NXP]
Dual bus buffer/line driver 3-state; 双总线缓冲器/线路驱动器三态
| 型号： | 74LVC2G125GM |
| 厂家： | 
NXP |
| 描述： | Dual bus buffer/line driver 3-state |
| 文件： | 总16页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC2G125
Dual bus buffer/line driver; 3-state
Product specification
2004 Sep 22
Supersedes data of 2004 Jan 09
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant input/output for interfacing with 5 V logic
• High noise immunity
The 74LVC2G125 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
This feature allows the use of these devices as translators
in a mixed 3.3 V and 5 V environment.
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
The 74LVC2G125 provides a dual non-inverting buffer/line
driver with 3-state output. The 3-state output is controlled
by the output enable input (pin nOE). A HIGH-level at
pin nOE causes the output to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay inputs nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
3.7
ns
ns
ns
ns
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.5
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.7
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.3
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.9
CI
input capacitance
2
pF
pF
pF
CPD
power dissipation capacitance per buffer output enabled; notes 1 and 2
output disabled; notes 1 and 2
18
5
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC
.
2004 Sep 22
2
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nY
nOE
L
nA
L
H
X
L
H
Z
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
MARKING
RANGE
74LVC2G125DP
74LVC2G125DC
74LVC2G125GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
8
8
8
TSSOP8
VSSOP8
XSON8
plastic
plastic
plastic
SOT505-2
SOT765-1
SOT833-1
V125
V25
V25
PINNING
PIN
1
SYMBOL
DESCRIPTION
1OE
1A
output enable input (active LOW)
data input
2
3
2Y
data output
4
GND
2A
ground (0 V)
5
data input
6
1Y
data output
7
2OE
VCC
output enable input (active LOW)
supply voltage
8
2004 Sep 22
3
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
125
1OE
1A
1
2
3
4
8
7
6
5
V
CC
1
2
3
4
8
7
6
5
1OE
1A
V
CC
2OE
1Y
2OE
1Y
125
2Y
GND
2A
2Y
001aab738
GND
2A
001aab739
Transparent top view
Fig.1 Pin configuration TSSOP8 and VSSOP8.
Fig.2 Pin configuration XSON8.
handbook, halfpage
1Y
2Y
1A
2
1
5
7
6
3
1OE
2A
2OE
MNA941
Fig.3 Logic symbol.
2004 Sep 22
4
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
V
V
V
VI
input voltage
0
0
5.5
VO
output voltage
VCC = 1.65 V to 5.5 V; enable
mode
VCC
VCC = 1.65 V to 5.5 V; disable
mode
0
5.5
V
VCC = 0 V; Power-down mode
0
5.5
+125
20
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0 V
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
mA
V
enable mode; notes 1 and 2
disable mode; notes 1 and 2
−0.5
−0.5
VCC + 0.5
+6.5
+6.5
±50
V
Power-down mode; notes 1 and 2 −0.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 V to VCC
−
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
300
−65
−
Ptot
Tamb = −40 °C to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2004 Sep 22
5
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
HIGH-level input voltage
LOW-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.45
0.3
2.7
0.4
3.0
0.55
0.55
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
V
1.2
1.9
2.2
2.3
3.8
−
−
V
IO = −8 mA
−
V
IO = −12 mA
IO = −24 mA
IO = −32 mA
VI = 5.5 V or GND
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
5.5
±0.1
±0.1
±5
±10
µA
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
3.6
−
current
VO = 5.5 V or GND
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
−
−
−
±0.1
0.1
5
±10
10
µA
µA
µA
ICC
∆ICC
quiescent supply current VI = VCC or GND;
IO = 0 A
5.5
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0 A
2.3 to 5.5
500
2004 Sep 22
6
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
TEST CONDITIONS
OTHER VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.70
0.45
0.60
0.80
0.80
2.7
3.0
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
V
0.95
1.7
1.9
2.0
3.4
−
−
V
IO = −8 mA
−
V
IO = −12 mA
IO = −24 mA
IO = −32 mA
VI = 5.5 V or GND
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
5.5
±20
±20
µA
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
3.6
−
current
VO = 5.5 V or GND
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
−
−
−
−
−
−
±20
40
µA
µA
µA
ICC
∆ICC
quiescent supply current VI = VCC or GND;
IO = 0 A
5.5
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0 A
2.3 to 5.5
5000
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Sep 22
7
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
AC CHARACTERISTICS
GND = 0 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH propagation delay nA to nY
see Figs 4 and 6
see Figs 5 and 6
see Figs 5 and 6
1.65 to 1.95
2.3 to 2.7
2.7
1.0
3.7
2.5
2.7
2.3
1.9
4.3
2.8
3.3
2.4
2.0
3.5
1.8
2.7
2.7
1.8
9.1
4.8
4.8
4.3
3.7
9.9
5.6
5.7
4.7
3.8
11.6
5.8
4.8
4.6
3.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5
1.0
0.5
0.5
1.5
1.0
1.5
0.5
0.5
1.0
0.5
1.0
1.0
0.5
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7
tPZH/tPZL
3-state output enable time
nOE to nY
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7
tPHZ/tPLZ
3-state output disable time
nOE to nY
3.0 to 3.6
4.5 to 5.5
Tamb = −40 °C to +125 °C
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay nA to nY
see Figs 4 and 6
see Figs 5 and 6
see Figs 5 and 6
1.65 to 1.95
2.3 to 2.7
2.7
1.0
0.5
1.0
0.5
0.5
1.5
1.0
1.5
0.5
0.5
1.0
0.5
1.0
1.0
0.5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
11.4
6.0
6.0
5.5
4.6
12.4
7.0
7.1
5.9
4.8
14.1
7.6
6.2
5.9
4.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7
3-state output enable time
nOE to nY
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7
3-state output disable time
nOE to nY
3.0 to 3.6
4.5 to 5.5
Note
1. All typical values are measured at Tamb = 25 °C.
2004 Sep 22
8
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
AC WAVEFORMS
V
handbook, halfpage
nA input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
MNA230
OL
INPUT
tr = tf
VCC
VM
VI
1.65 V to 1.95 V 0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.3 V to 2.7 V
2.7 V
0.5 × VCC VCC
1.5 V
1.5 V
2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
0.5 × VCC VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 The input (nA) to output (nY) propagation delays and the output transition times.
2004 Sep 22
9
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA362
INPUT
VCC
VM
VI
tr = tf
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.65 V to 1.95 V 0.5 × VCC VCC
V
X = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.15 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.15 V at VCC < 2.7 V.
2.3 V to 2.7 V
2.7 V
0.5 × VCC VCC
1.5 V
1.5 V
2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
VOL and VOH are typical output voltage drop that occur with the output
load.
0.5 × VCC VCC
Fig.5 3-state enable and disable times.
2004 Sep 22
10
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
CL
RL
1 kΩ
1.65 V to 1.95 V VCC
30 pF
30 pF
50 pF
50 pF
50 pF
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
R
L = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2004 Sep 22
11
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2004 Sep 22
12
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2004 Sep 22
13
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.0
0.9
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-15
04-07-22
SOT833-1
- - -
MO-252
2004 Sep 22
14
Philips Semiconductors
Product specification
Dual bus buffer/line driver; 3-state
74LVC2G125
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Sep 22
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/04/pp16
Date of release: 2004 Sep 22
Document order number: 9397 750 13777
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