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74LVC2G126GT [NXP]

Dual bus buffer/line driver; 3-state; 双总线缓冲器/线路驱动器;三态
74LVC2G126GT
型号： 74LVC2G126GT
厂家： NXP    NXP
描述：

Dual bus buffer/line driver; 3-state
双总线缓冲器/线路驱动器;三态

驱动器
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中文：  中文翻译
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74LVC2G126  
Dual bus buffer/line driver; 3-state  
Rev. 06 — 7 September 2007  
Product data sheet  
1. General description  
The 74LVC2G126 provides a dual non-inverting buffer/line driver with 3-state output. The  
3-state output is controlled by the output enable input (pin nOE). A LOW-level at pin nOE  
causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all  
inputs makes the circuit highly tolerant of slower input rise and fall times.  
Inputs can be driven from either 3.3 V or 5 V devices. These feature allows the use of  
these devices as translators in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features  
■ Wide supply voltage range from 1.65 V to 5.5 V  
■ 5 V tolerant input/output for interfacing with 5 V logic  
■ High noise immunity  
■ Complies with JEDEC standard:  
◆ JESD8-7 (1.65 V to 1.95 V)  
◆ JESD8-5 (2.3 V to 2.7 V)  
◆ JESD8-B/JESD36 (2.7 V to 3.6 V)  
■ ESD protection:  
◆ HBM JESD22-A114E exceeds 2000 V  
◆ MM JESD22-A115-A exceeds 200 V  
■ ±24 mA output drive (VCC = 3.0 V)  
■ CMOS low power consumption  
■ Latch-up performance exceeds 250 mA  
■ Direct interface with TTL levels  
■ Inputs accept voltages up to 5 V  
■ Multiple package options  
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC2G126DP  
74LVC2G126DC  
74LVC2G126GT  
74LVC2G126GM  
−40 °C to +125 °C  
−40 °C to +125 °C  
−40 °C to +125 °C  
−40 °C to +125 °C  
TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm; lead length 0.5 mm  
SOT505-2  
VSSOP8  
XSON8  
XQFN8  
plastic very thin shrink small outline package; 8 leads; SOT765-1  
body width 2.3 mm  
plastic extremely thin small outline package; no leads; SOT833-1  
8 terminals; body 1 × 1.95 × 0.5 mm  
plastic extremely thin quad flat package; no leads;  
SOT902-1  
8 terminals; body 1.6 × 1.6 × 0.5 mm  
4. Marking  
Table 2.  
Marking  
Type number  
Marking code  
74LVC2G126DP  
74LVC2G126DC  
74LVC2G126GT  
74LVC2G126GM  
V26  
V26  
V26  
V26  
5. Functional diagram  
1Y  
2Y  
1A  
2
6
3
1OE  
1
nY  
nA  
2A  
5
2OE  
7
nOE  
mna946  
mna234  
Fig 1. Logic symbol  
Fig 2. Logic diagram (one gate)  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
2 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
6. Pinning information  
6.1 Pinning  
74LVC2G126  
1
2
3
4
8
7
6
5
1OE  
1A  
V
CC  
2OE  
1Y  
2Y  
GND  
2A  
001aab740  
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)  
74LVC2G126  
terminal 1  
index area  
74LVC2G126  
2OE  
1
1OE  
1A  
1
2
3
4
8
7
6
5
V
CC  
7
6
5
1OE  
1A  
2OE  
1Y  
1Y  
2A  
2
3
2Y  
2Y  
GND  
2A  
001aaf056  
001aab741  
Transparent top view  
Transparent top view  
Fig 4. Pin configuration SOT833-1 (XSON8)  
Fig 5. Pin configuration SOT902-1 (XQFN8)  
6.2 Pin description  
Table 3.  
Symbol  
Pin description  
Pin  
Description  
SOT505-2, SOT765-1, SOT902-1  
SOT833-1  
1OE  
1A  
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
output enable input (active HIGH)  
data input  
2Y  
data output  
GND  
2A  
ground (0 V)  
data input  
1Y  
data output  
2OE  
VCC  
output enable input (active HIGH)  
supply voltage  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
3 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
7. Functional description  
Table 4.  
Function table[1]  
Input  
nOE  
H
Output  
nA  
L
nY  
L
H
H
H
Z
L
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
−0.5  
−50  
−0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
VI  
+6.5  
±50  
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
Active mode  
mA  
V
[1][2]  
[1][2]  
VO  
−0.5  
−0.5  
-
VCC + 0.5  
+6.5  
±50  
Power-down mode  
VO = 0 V to VCC  
V
IO  
output current  
mA  
mA  
mA  
mW  
°C  
ICC  
IGND  
Ptot  
Tstg  
supply current  
-
+100  
-
ground current  
−100  
-
[3]  
total power dissipation  
storage temperature  
Tamb = −40 °C to +125 °C  
300  
−65  
+150  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.  
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.  
For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.  
9. Recommended operating conditions  
Table 6.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
5.5  
Unit  
V
supply voltage  
input voltage  
output voltage  
1.65  
-
-
-
-
-
-
-
VI  
0
5.5  
V
VO  
Active mode  
0
VCC  
5.5  
V
VCC = 0 V; Power-down mode  
0
V
Tamb  
ambient temperature  
−40  
+125  
20  
°C  
ns/V  
ns/V  
∆t/∆V  
input transition rise and fall rate VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
-
-
10  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
4 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
10. Static characteristics  
Table 7.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
Tamb = −40 °C to +85 °C  
VIH  
HIGH-level input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.65VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
-
2.0  
-
0.7VCC  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.35VCC  
0.7  
0.8  
0.3VCC  
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
-
-
-
-
-
-
-
-
-
-
-
-
0.1  
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
0.45  
0.3  
0.4  
0.55  
0.55  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = −100 µA; VCC = 1.65 V to 5.5 V  
IO = −4 mA; VCC = 1.65 V  
V
CC − 0.1  
-
-
V
1.2  
1.9  
2.2  
2.3  
3.8  
-
-
-
V
IO = −8 mA; VCC = 2.3 V  
-
-
V
IO = −12 mA; VCC = 2.7 V  
-
-
V
IO = −24 mA; VCC = 3.0 V  
-
-
V
IO = −32 mA; VCC = 4.5 V  
-
-
V
II  
input leakage current  
VI = 5.5 V or GND; VCC = 0 V to 5.5 V  
±0.1  
±0.1  
±5  
±10  
µA  
µA  
IOZ  
OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND;  
CC = 3.6 V  
-
V
IOFF  
ICC  
power-off leakage current VI or VO = 5.5 V; VCC = 0 V  
supply current VI = 5.5 V or GND;  
CC = 1.65 V to 5.5 V; IO = 0 A  
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;  
CC = 2.3 V to 5.5 V  
-
-
±0.1  
±10  
µA  
µA  
0.1  
10  
V
∆ICC  
-
-
5
2
500  
-
µA  
V
CI  
input capacitance  
pF  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
5 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
Tamb = −40 °C to +125 °C  
VIH  
HIGH-level input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.65VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
-
2.0  
-
0.7VCC  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.35VCC  
0.7  
0.8  
0.3VCC  
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
-
-
-
-
-
-
-
-
-
-
-
-
0.1  
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
0.70  
0.45  
0.60  
0.80  
0.80  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = −100 µA; VCC = 1.65 V to 5.5 V  
IO = −4 mA; VCC = 1.65 V  
V
CC − 0.1  
-
-
-
-
-
-
-
-
-
V
0.95  
1.7  
1.9  
2.0  
3.4  
-
-
V
IO = −8 mA; VCC = 2.3 V  
-
V
IO = −12 mA; VCC = 2.7 V  
-
V
IO = −24 mA; VCC = 3.0 V  
-
V
IO = −32 mA; VCC = 4.5 V  
-
V
II  
input leakage current  
VI = 5.5 V or GND; VCC = 0 V to 5.5 V  
±20  
±20  
µA  
µA  
IOZ  
OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND;  
CC = 3.6 V  
-
V
IOFF  
ICC  
power-off leakage current VI or VO = 5.5 V; VCC = 0 V  
supply current VI = 5.5 V or GND;  
CC = 1.65 V to 5.5 V; IO = 0 A  
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;  
CC = 2.3 V to 5.5 V  
-
-
-
-
±20  
µA  
µA  
40  
V
∆ICC  
-
-
5
mA  
V
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
6 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8.  
Symbol Parameter Conditions −40 °C to +85 °C  
−40 °C to +125 °C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
[3]  
[4]  
[5]  
tpd  
propagation delay nA to nY; see Figure 6  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
1.0  
0.5  
1.0  
0.5  
0.5  
3.9  
2.6  
2.8  
2.4  
1.9  
9.8  
4.9  
4.7  
4.3  
3.2  
1.0  
0.5  
1.0  
0.5  
0.5  
12.3  
6.3  
5.9  
5.4  
4.0  
ns  
ns  
ns  
ns  
ns  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
ten  
enable time  
nOE to nY; see Figure 7  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.0  
1.0  
1.0  
0.5  
4.1  
2.6  
2.8  
2.4  
1.8  
10.0  
5.0  
4.7  
4.1  
3.1  
1.0  
1.0  
1.0  
1.0  
0.5  
12.5  
6.3  
5.9  
5.1  
3.9  
ns  
ns  
ns  
ns  
ns  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
nOE to nY; see Figure 7  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
tdis  
disable time  
1.0  
0.5  
1.5  
1.0  
0.5  
3.3  
1.9  
3.0  
2.5  
1.8  
12.6  
5.7  
4.8  
4.4  
3.3  
1.0  
0.5  
1.5  
1.0  
0.5  
15.4  
7.5  
6.2  
5.7  
4.4  
ns  
ns  
ns  
ns  
ns  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
CPD  
power dissipation per buffer; VI = GND to VCC  
capacitance  
output enabled  
-
-
17  
5
-
-
-
-
-
-
pF  
pF  
output disabled  
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.  
[2] tpd is the same as tPLH and tPHL  
[3] ten is the same as tPZH and tPZL  
[4] tdis is the same as tPLZ and tPHZ  
[5] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
∑(CL × VCC2 × fo) = sum of outputs.  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
7 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
12. Waveforms  
V
I
V
nA input  
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
V
OL  
mna230  
Measurement points are given in Table 9.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 6. The data input (nA) to output (nY) propagation delays  
V
I
nOE input  
V
M
t
GND  
t
PLZ  
PZL  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PZH  
PHZ  
V
OH  
V
Y
output  
V
HIGH-to-OFF  
OFF-to-HIGH  
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
mna949  
Measurement points are given in Table 9.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 7. 3-state enable and disable times  
Table 9.  
Measurement points  
Supply voltage  
VCC  
Input  
VM  
Output  
VM  
VX  
VY  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5VCC  
0.5VCC  
1.5 V  
1.5 V  
0.5VCC  
0.5VCC  
0.5VCC  
1.5 V  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOL + 0.3 V  
V
V
V
V
V
OH − 0.15 V  
OH − 0.15 V  
OH − 0.3 V  
OH − 0.3 V  
OH − 0.3 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
0.5VCC  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
8 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Test data is given in Table 10.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 8. Load circuitry for switching times  
Table 10. Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr, tf  
RL  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ  
2VCC  
2VCC  
6 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
≤ 2.0 ns  
≤ 2.0 ns  
≤ 2.5 ns  
≤ 2.5 ns  
≤ 2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
GND  
open  
GND  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
GND  
6 V  
open  
GND  
2VCC  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
9 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
13. Package outline  
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm  
SOT505-2  
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
detail X  
1
4
e
w
M
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
max.  
0.15  
0.00  
0.95  
0.75  
0.38  
0.22  
0.18  
0.08  
3.1  
2.9  
3.1  
2.9  
4.1  
3.9  
0.47  
0.33  
0.70  
0.35  
8°  
0°  
mm  
1.1  
0.65  
0.25  
0.5  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-01-16  
SOT505-2  
- - -  
Fig 9. Package outline SOT505-2 (TSSOP8)  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
10 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm  
SOT765-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )  
3
pin 1 index  
θ
L
p
L
detail X  
1
4
e
w
M
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT  
v
w
y
Z
θ
1
2
3
p
E
max.  
0.15  
0.00  
0.85  
0.60  
0.27  
0.17  
0.23  
0.08  
2.1  
1.9  
2.4  
2.2  
3.2  
3.0  
0.40  
0.15  
0.21  
0.19  
0.4  
0.1  
8°  
0°  
mm  
1
0.5  
0.12  
0.4  
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-06-07  
SOT765-1  
MO-187  
Fig 10. Package outline SOT765-1 (VSSOP8)  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
11 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm  
SOT833-1  
b
1
2
3
4
4×  
(2)  
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×  
(2)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.25  
0.17  
2.0  
1.9  
1.05  
0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.6  
0.5  
Notes  
1. Including plating thickness.  
2. Can be visible in some manufacturing processes.  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
JEITA  
- - -  
04-07-22  
04-11-09  
SOT833-1  
- - -  
MO-252  
Fig 11. Package outline SOT833-1 (XSON8)  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
12 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm  
SOT902-1  
D
B
A
terminal 1  
index area  
E
A
A
1
detail X  
e
L
1
e
C
y
C
1
y
L
M
M
v
C
C
A
B
4
w
5
6
7
3
2
metal area  
not for soldering  
e
1
b
e
1
1
terminal 1  
index area  
8
X
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
UNIT  
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max  
0.05 0.25 1.65 1.65  
0.00 0.15 1.55 1.55  
0.35 0.15  
0.25 0.05  
mm  
0.5  
0.55  
0.5  
0.1  
0.05 0.05 0.05  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
MO-255  
JEITA  
05-11-16  
05-11-25  
SOT902-1  
- - -  
- - -  
Fig 12. Package outline SOT902-1 (XQFN8)  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
13 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
14. Abbreviations  
Table 11. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MM  
Machine Model  
TTL  
Transistor-Transistor Logic  
15. Revision history  
Table 12. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74LVC2G126_6  
Modifications:  
20070907  
Product data sheet  
-
74LVC2G126_5  
• In Section 10 “Static characteristics”, changed conditions for input leakage and supply current.  
74LVC2G126_5  
74LVC2G126_4  
74LVC2G126_3  
74LVC2G126_2  
74LVC2G126_1  
20061006  
20050201  
20040922  
20030901  
20030310  
Product data sheet  
Product specification  
Product specification  
Product specification  
Product specification  
-
-
-
-
-
74LVC2G126_4  
74LVC2G126_3  
74LVC2G126_2  
74LVC2G126_1  
-
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
14 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of a NXP Semiconductors product can reasonably be expected to  
16.2 Definitions  
result in personal injury, death or severe property or environmental damage.  
NXP Semiconductors accepts no liability for inclusion and/or use of NXP  
Semiconductors products in such equipment or applications and therefore  
such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
16.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
17. Contact information  
For additional information, please visit: http://www.nxp.com  
For sales office addresses, send an email to: salesaddresses@nxp.com  
74LVC2G126_6  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 06 — 7 September 2007  
15 of 16  
74LVC2G126  
NXP Semiconductors  
Dual bus buffer/line driver; 3-state  
18. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14  
8
9
10  
11  
12  
13  
14  
15  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 15  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2007.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 7 September 2007  
Document identifier: 74LVC2G126_6  

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