74LVC2G17GW-T [NXP]
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| 型号： | 74LVC2G17GW-T |
| 厂家： | 
NXP |
| 描述： | 暂无描述 触发器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G17
Dual non-inverting Schmitt trigger with 5 V tolerant input
Rev. 04 — 9 October 2006
Product data sheet
1. General description
The 74LVC2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger action. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD-8B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114-D exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low-power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
I Wave and pulse shapers for highly noisy environments
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
Name
SC-88
SC-74
XSON6
Description
Version
74LVC2G17GW
74LVC2G17GV
74LVC2G17GM
plastic surface-mounted package; 6 leads
SOT363
plastic surface-mounted package (TSOP6); 6 leads SOT457
plastic extremely thin small outline package;
SOT886
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
74LVC2G17GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package;
SOT891
no leads; 6 terminals; body 1 × 1 × 0.5 mm
5. Marking
Table 2.
Marking codes
Type number
74LVC2G17GW
74LVC2G17GV
74LVC2G17GM
74LVC2G17GF
Marking code
VV
VV
VV
VV
6. Functional diagram
1
3
6
4
1
3
1A
2A
1Y
2Y
6
4
mnb066
mnb067
Fig 1. Logic symbol
Fig 2. IEC logic symbol
1A
1Y
2A
2Y
mnb068
Fig 3. Logic diagram
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
2 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
7. Pinning information
7.1 Pinning
74LVC2G17
74LVC2G17
1A
GND
2A
1
2
3
6
5
4
1Y
74LVC2G17
1
2
3
6
5
4
1A
GND
2A
1Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
V
CC
V
CC
2Y
2Y
2Y
001aaf079
001aaf080
Transparent top view
Transparent top view
001aaf078
Fig 4. Pin configuration SOT363
and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
7.2 Pin description
Table 3.
Symbol
1A
Pin description
Pin
Description
data input
1
2
3
4
5
6
GND
2A
ground (0 V)
data input
2Y
data output
supply voltage
data input
VCC
1Y
8. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nY
L
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
3 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+6.5
−50
Unit
V
supply voltage
−0.5
input clamping current
input voltage
VI < 0 V
-
mA
V
[1]
VI
−0.5
+6.5
−50
IOK
output clamping current
output voltage
VO < 0 V
-
mA
V
[1][2]
[1][2]
VO
Active mode
−0.5
VCC + 0.5
+6.5
±50
Power-down mode
VO = 0 V to VCC
−0.5
V
IO
output current
-
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-
−100
+150
300
storage temperature
total power dissipation
−65
[3]
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
0
Typ
Max
5.5
Unit
supply voltage
input voltage
-
-
-
-
V
VI
5.5
V
VO
output voltage
ambient temperature
0
VCC
+125
V
Tamb
−40
°C
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
0.45
0.3
0.4
0.55
0.55
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
4 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
VI = VCC or GND; IO = 0 A;
V
CC − 0.1 -
-
V
1.2
1.9
2.2
2.3
3.8
-
-
-
V
-
-
V
-
-
V
-
-
V
-
-
V
II
input leakage current
power-off leakage current
supply current
±0.1
±0.1
0.1
±5
±10
10
µA
µA
µA
IOFF
ICC
-
-
V
CC = 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
∆ICC
additional supply current
input capacitance
-
-
5
500
-
µA
V
CI
3.5
pF
Tamb = −40 °C to +125 °C
VOL LOW-level output voltage
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
0.70
0.45
0.60
0.80
0.80
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VIH or VIL
VOH
HIGH-level output voltage
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
VI = VCC or GND; IO = 0 A;
V
CC − 0.1 -
-
V
0.95
1.7
1.9
2.0
3.4
-
-
-
V
-
-
V
-
-
V
-
-
V
-
-
V
II
input leakage current
power-off leakage current
supply current
±0.1
±20
±20
40
µA
µA
µA
IOFF
ICC
-
-
-
-
V
CC = 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
∆ICC
additional supply current
-
-
5
mA
V
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
5 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 1.65 V to 1.95 V
1.5
1.0
1.0
1.0
1.0
-
5.6
3.7
10.5
6.5
6.5
5.7
4.3
-
1.5
1.0
1.0
1.0
1.0
-
13.1
8.5
8.5
7.1
5.4
-
ns
ns
ns
ns
ns
pF
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
3.8
VCC = 3.0 V to 3.6 V
3.6
VCC = 4.5 V to 5.5 V
2.7
[3]
CPD
power dissipation per buffer; VCC = 3.3 V;
16.3
capacitance
VI = GND to VCC
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
13. Waveforms
V
I
nA input
V
M
V
M
GND
t
t
PLH
PHL
V
OH
V
V
M
nY output
M
V
OL
mnb072
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The input (nA) to output (nY) propagation delays and the output transition times
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
6 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
Table 9.
Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
mna616
Measurement points are given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
7 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
14. Transfer characteristics
Table 11. Transfer characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VT+
VT−
VH
positive-going
threshold voltage
see Figure 9 and Figure 10
VCC = 1.8 V
0.70
1.00
1.30
1.90
2.20
1.10
1.40
1.76
2.47
2.91
1.50
1.80
2.20
3.10
3.60
0.70
1.00
1.30
1.90
2.20
1.70
2.00
2.40
3.30
3.80
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
negative-going
threshold voltage
see Figure 9 and Figure 10
VCC = 1.8 V
0.25
0.40
0.60
1.00
1.20
0.61
0.80
1.04
1.55
1.86
0.90
1.15
1.50
2.00
2.30
0.25
0.40
0.60
1.00
1.20
1.10
1.35
1.70
2.20
2.50
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
hysteresis voltage (VT+ − VT−); see Figure 9,
Figure 10 and Figure 11
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.15
0.25
0.40
0.60
0.70
0.49
0.60
0.73
0.92
1.02
1.00
1.10
1.20
1.50
1.70
0.15
0.25
0.40
0.60
0.70
1.20
1.30
1.40
1.70
1.90
V
V
V
V
V
[1] All typical values are measured at Tamb = 25 °C.
15. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mnb155
V
H
V
V
T+
T−
mnb154
VT+ and VT− limits at 70 % and 20 %.
Fig 9. Transfer characteristic
Fig 10. Definition of VT+, VT− and VH
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
8 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
mnb071
14
I
CC
(mA)
12
10
8
6
4
2
0
0
0.5
1
1.5
2
V (V)
I
VCC = 3.0 V.
Fig 11. Typical transfer characteristic
mnb156
50
I
CC
(mA)
(1)
40
30
20
(2)
10
0
2
3
4
5
6
V
(V)
CC
(1) Positive-going edge
(2) Negative-going edge
Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
Fig 12. Average ICC as a function of VCC
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
9 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
16. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 13. Package outline SOT363 (SC-88)
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
10 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-11-07
06-03-16
SOT457
SC-74
Fig 14. Package outline SOT457 (SC-74)
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
11 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 15. Package outline SOT886 (XSON6)
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
12 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
L
L
1
e
6
5
4
e
1
e
1
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-03-11
05-04-06
SOT891
Fig 16. Package outline SOT891 (XSON6)
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
13 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
17. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
18. Revision history
Table 13. Revision history
Document ID
74LVC2G17_4
Modifications:
Release date
20061009
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC2G17_3
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74LVC2G17GF (SOT891 package).
74LVC2G17_3
74LVC2G17_2
74LVC2G17_1
20050926
20040908
20030813
Product data sheet
Product specification
Product specification
-
-
-
74LVC2G17_2
74LVC2G17_1
-
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
14 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
19.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC2G17_4
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 October 2006
15 of 16
74LVC2G17
NXP Semiconductors
Dual non-inverting Schmitt trigger with 5 V tolerant input
21. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transfer characteristics. . . . . . . . . . . . . . . . . . . 8
Waveforms transfer characteristics. . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
9
10
11
12
13
14
15
16
17
18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 October 2006
Document identifier: 74LVC2G17_4
相关型号：
74LVC2G240DC-G
Dual inverting buffer/line driver; 3-state - Description: 3.3V Dual Buffer/Line Driver; Inverting (3-State) ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.5@3.3V ns; Voltage: 1.65 - 5.5
NXP
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