74LVC2G38GM-G [NXP]
IC LVC/LCX/Z SERIES, DUAL 2-INPUT NAND GATE, PQCC8, 1.6 X 1.6 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT-902-1, QFN-8, Gate;
| 型号： | 74LVC2G38GM-G |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, DUAL 2-INPUT NAND GATE, PQCC8, 1.6 X 1.6 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT-902-1, QFN-8, Gate 栅 输入元件 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G38
Dual 2-input NAND gate (open drain)
Rev. 04 — 16 May 2006
Product data sheet
1. General description
The 74LVC2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
The 74LVC2G38 provides the 2-input NAND function.
The outputs of the 74LVC2G38 devices are open drain and can be connected to other
open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND
functions.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant outputs for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM EIA/JESD22-A114-C exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Open-drain outputs
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
Name
Description
Version
74LVC2G38DP
74LVC2G38DC
74LVC2G38GT
74LVC2G38GM
TSSOP8
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
VSSOP8
XSON8
XQFN8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
SOT833-1
SOT902-1
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package;
no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking code
Type number
74LVC2G38DP
74LVC2G38DC
74LVC2G38GT
74LVC2G38GM
Marking code
Y38
Y38
Y38
Y38
5. Functional diagram
1
&
7
3
1
2
1A
1B
1Y
7
3
2
5
6
2A
2B
5
2Y
&
6
mnb129
mnb130
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Y
A
B
GND
mnb131
Fig 3. Functional diagram (one gate)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
2 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
6. Pinning information
6.1 Pinning
74LVC2G38
1A
1B
1
2
3
4
8
7
6
5
V
CC
74LVC2G38
1Y
2B
2A
1
2
3
4
8
7
6
5
1A
1B
V
CC
1Y
2B
2A
2Y
2Y
GND
001aab829
GND
001aab830
Transparent top view
Fig 4. Pin configuration TSSOP8 and
VSSOP8
Fig 5. Pin configuration XSON8
74LVC2G38
terminal 1
index area
1Y
1
7
6
5
1A
1B
2Y
2B
2A
2
3
001aae979
Transparent top view
Fig 6. Pin configuration XQFN8
6.2 Pin description
Table 3.
Symbol Pin
TSSOP8, VSSOP8 XSON8
Pin description
Description
XQFN8
1A
1
2
3
4
5
1
2
3
4
5
7
6
5
4
3
data input 1A
data input 1B
data output 2Y
ground (0 V)
data input 2A
1B
2Y
GND
2A
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
3 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
Table 3.
Pin description …continued
Symbol Pin
TSSOP8, VSSOP8 XSON8
Description
XQFN8
2B
6
7
8
6
7
8
2
1
8
data input 2B
data output 1Y
supply voltage
1Y
VCC
7. Functional description
7.1 Function table
Table 4.
Function table[1]
Input
nA
L
Output
nB
L
nY
Z
L
H
L
Z
H
Z
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+6.5
+6.5
+6.5
+6.5
−50
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
−0.5
[1]
[1][2]
[1][2]
−0.5
V
VO
Active mode
−0.5
V
Power-down mode
VI < 0 V
−0.5
V
IIK
input clamping current
output clamping current
output current
-
mA
mA
mA
mA
mA
°C
IOK
IO
VO > VCC or VO < 0 V
VO = 0 V to VCC
-
±50
-
±50
ICC
IGND
Tstg
Ptot
quiescent supply current
ground current
-
100
-
−100
+150
300
storage temperature
total power dissipation
−65
[3]
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
4 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
0
Typ
Max
5.5
5.5
VCC
5.5
5.5
+125
20
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
-
-
-
-
-
-
-
-
V
VO
Active mode
0
V
disable mode
0
V
Power-down mode
0
V
Tamb
ambient temperature
−40
0
°C
ns/V
ns/V
∆t/∆V
input transition rise
and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
0
10
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-state input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-state output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
0.08
0.14
0.19
0.37
0.43
±0.1
±0.1
0.1
0.45
0.3
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
0.4
V
0.55
0.55
±5
V
V
ILI
input leakage current
µA
µA
µA
µA
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
±10
10
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V
∆ICC
additional quiescent
supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
5
500
V
Ci
input capacitance
-
2.5
-
pF
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
5 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-state input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-state output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
0.70
0.45
0.60
0.80
0.80
±20
±20
40
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
V
V
V
ILI
input leakage current
µA
µA
µA
µA
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V
∆ICC
additional quiescent
supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
5000
V
[1] All typical values are measured at Tamb = 25 °C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Tamb = −40 °C to +85 °C[1]
tPZL, tPLZ propagation delay inputs nA
and nB to output nY
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.2
0.7
0.7
0.7
0.5
-
3.0
1.8
2.5
2.1
1.5
5
8.6
4.8
4.4
4.1
3.3
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[2]
CPD
power dissipation capacitance per gate; VCC = 3.3 V;
VI = GND to VCC
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
6 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Tamb = −40 °C to +125 °C
tPZL, tPLZ propagation delay inputs nA
and nB to output nY
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.2
0.7
0.7
0.7
0.5
-
-
-
-
-
10.8
6.0
5.5
5.2
4.2
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[1] All typical values are measured at nominal supply voltage and at Tamb = 25 °C.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
V
I
nA, nB input
V
t
M
GND
t
PZL
PLZ
V
CC
nY output
V
M
V
V
X
OL
mnb132
Measurement points are given in Table 9
Fig 7. Inputs nA and nB to output nY propagation delay times
Table 9. Measurement points
Supply voltage
VCC
Input
Output
VM
VX
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
7 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 10
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPLZ, tPZL
2 × VCC
2 × VCC
6 V
1.65 V to 1.95 V VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
8 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 9. Package outline SOT505-2 (TSSOP8)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
9 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
10 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
Fig 11. Package outline SOT833-1 (XSON8)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
11 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
C
1
y
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-16
05-11-25
SOT902-1
- - -
- - -
Fig 12. Package outline SOT902-1 (XQFN8)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
12 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
74LVC2G38_4
Modifications:
Release date
20060516
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC2G38_3
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
• Added: type number 74LVC2G38GM (XQFN8 package)
74LVC2G38_3
(9397 750 14538)
20050201
20041018
20031027
Product specification
Product specification
Product specification
-
-
-
74LVC2G38_2
74LVC2G38_2
(9397 750 13785)
74LVC2G38_1
-
74LVC2G38_1
(9397 750 11955)
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
13 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
malfunction of a Philips Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74LVC2G38_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 16 May 2006
14 of 15
74LVC2G38
Philips Semiconductors
Dual 2-input NAND gate (open drain)
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 16 May 2006
Document identifier: 74LVC2G38_4
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